shader/shift: Implement SHF_LEFT_{IMM,R}

Shifts a pair of registers to the left and returns the high register.
This commit is contained in:
ReinUsesLisp 2020-02-01 02:57:01 -03:00
parent 2db7adc42a
commit 017474c3f8
2 changed files with 89 additions and 10 deletions

View file

@ -624,6 +624,19 @@ enum class ShuffleOperation : u64 {
Bfly = 3, // shuffleXorNV Bfly = 3, // shuffleXorNV
}; };
enum class ShfType : u64 {
Bits32 = 0,
U64 = 2,
S64 = 3,
};
enum class ShfXmode : u64 {
None = 0,
HI = 1,
X = 2,
XHI = 3,
};
union Instruction { union Instruction {
constexpr Instruction& operator=(const Instruction& instr) { constexpr Instruction& operator=(const Instruction& instr) {
value = instr.value; value = instr.value;
@ -775,6 +788,13 @@ union Instruction {
BitField<39, 1, u64> wrap; BitField<39, 1, u64> wrap;
} shr; } shr;
union {
BitField<37, 2, ShfType> type;
BitField<48, 2, ShfXmode> xmode;
BitField<50, 1, u64> wrap;
BitField<20, 6, u64> immediate;
} shf;
union { union {
BitField<39, 5, u64> shift_amount; BitField<39, 5, u64> shift_amount;
BitField<48, 1, u64> negate_b; BitField<48, 1, u64> negate_b;

View file

@ -10,8 +10,30 @@
namespace VideoCommon::Shader { namespace VideoCommon::Shader {
using std::move;
using Tegra::Shader::Instruction; using Tegra::Shader::Instruction;
using Tegra::Shader::OpCode; using Tegra::Shader::OpCode;
using Tegra::Shader::ShfType;
using Tegra::Shader::ShfXmode;
namespace {
Node Shift(OperationCode opcode, Node value, Node shift) {
Node is_full = Operation(OperationCode::LogicalIEqual, shift, Immediate(32));
Node shifted = Operation(opcode, move(value), move(shift));
return Operation(OperationCode::Select, move(is_full), Immediate(0), move(shifted));
}
Node ClampShift(Node shift, s32 size = 32) {
shift = Operation(OperationCode::IMax, move(shift), Immediate(0));
return Operation(OperationCode::IMin, move(shift), Immediate(size));
}
Node WrapShift(Node shift, s32 size = 32) {
return Operation(OperationCode::UBitwiseAnd, move(shift), Immediate(size - 1));
}
} // Anonymous namespace
u32 ShaderIR::DecodeShift(NodeBlock& bb, u32 pc) { u32 ShaderIR::DecodeShift(NodeBlock& bb, u32 pc) {
const Instruction instr = {program_code[pc]}; const Instruction instr = {program_code[pc]};
@ -32,25 +54,62 @@ u32 ShaderIR::DecodeShift(NodeBlock& bb, u32 pc) {
case OpCode::Id::SHR_C: case OpCode::Id::SHR_C:
case OpCode::Id::SHR_R: case OpCode::Id::SHR_R:
case OpCode::Id::SHR_IMM: { case OpCode::Id::SHR_IMM: {
if (instr.shr.wrap) { op_b = instr.shr.wrap ? WrapShift(move(op_b)) : ClampShift(move(op_b));
op_b = Operation(OperationCode::UBitwiseAnd, std::move(op_b), Immediate(0x1f));
} else {
op_b = Operation(OperationCode::IMax, std::move(op_b), Immediate(0));
op_b = Operation(OperationCode::IMin, std::move(op_b), Immediate(31));
}
Node value = SignedOperation(OperationCode::IArithmeticShiftRight, instr.shift.is_signed, Node value = SignedOperation(OperationCode::IArithmeticShiftRight, instr.shift.is_signed,
std::move(op_a), std::move(op_b)); move(op_a), move(op_b));
SetInternalFlagsFromInteger(bb, value, instr.generates_cc); SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
SetRegister(bb, instr.gpr0, std::move(value)); SetRegister(bb, instr.gpr0, move(value));
break; break;
} }
case OpCode::Id::SHL_C: case OpCode::Id::SHL_C:
case OpCode::Id::SHL_R: case OpCode::Id::SHL_R:
case OpCode::Id::SHL_IMM: { case OpCode::Id::SHL_IMM: {
const Node value = Operation(OperationCode::ILogicalShiftLeft, op_a, op_b); Node value = Operation(OperationCode::ILogicalShiftLeft, op_a, op_b);
SetInternalFlagsFromInteger(bb, value, instr.generates_cc); SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
SetRegister(bb, instr.gpr0, value); SetRegister(bb, instr.gpr0, move(value));
break;
}
case OpCode::Id::SHF_LEFT_R:
case OpCode::Id::SHF_LEFT_IMM: {
UNIMPLEMENTED_IF(instr.generates_cc);
UNIMPLEMENTED_IF_MSG(instr.shf.xmode != ShfXmode::None, "xmode={}",
static_cast<int>(instr.shf.xmode.Value()));
if (instr.is_b_imm) {
op_b = Immediate(static_cast<u32>(instr.shf.immediate));
}
const s32 size = instr.shf.type == ShfType::Bits32 ? 32 : 64;
Node shift = instr.shf.wrap ? WrapShift(move(op_b), size) : ClampShift(move(op_b), size);
Node negated_shift = Operation(OperationCode::INegate, shift);
Node low_shift = Operation(OperationCode::IAdd, move(negated_shift), Immediate(32));
Node low = move(op_a);
Node high = GetRegister(instr.gpr39);
Node value;
if (instr.shf.type == ShfType::Bits32) {
high = Shift(OperationCode::ILogicalShiftLeft, move(high), move(shift));
low = Shift(OperationCode::ILogicalShiftRight, move(op_a), move(low_shift));
value = Operation(OperationCode::IBitwiseOr, move(high), move(low));
} else {
// These values are used when the shift value is less than 32
Node less_low = Operation(OperationCode::ILogicalShiftRight, low, low_shift);
Node less_high = Operation(OperationCode::ILogicalShiftLeft, high, shift);
Node less = Operation(OperationCode::IBitwiseOr, move(less_low), move(less_high));
// And these when it's larger than or 32
Node reduced = Operation(OperationCode::IAdd, shift, Immediate(-32));
Node greater = Shift(OperationCode::ILogicalShiftLeft, move(low), move(reduced));
Node is_less = Operation(OperationCode::LogicalILessThan, shift, Immediate(32));
Node is_zero = Operation(OperationCode::LogicalIEqual, move(shift), Immediate(0));
value = Operation(OperationCode::Select, move(is_less), move(less), move(greater));
value = Operation(OperationCode::Select, move(is_zero), move(high), move(value));
}
SetRegister(bb, instr.gpr0, move(value));
break; break;
} }
default: default: