mirror of
https://github.com/yuzu-mirror/yuzu.git
synced 2024-09-07 17:09:09 +01:00
GPU: Partially implemented the Maxwell DMA engine.
Only tiled->linear and linear->tiled copies that aren't offsetted are supported for now. Queries are not supported. Swizzled copies are not supported.
This commit is contained in:
parent
281fd881a0
commit
987a170665
7 changed files with 237 additions and 1 deletions
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@ -9,6 +9,8 @@ add_library(video_core STATIC
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engines/maxwell_3d.h
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engines/maxwell_compute.cpp
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engines/maxwell_compute.h
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engines/maxwell_dma.cpp
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engines/maxwell_dma.h
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engines/shader_bytecode.h
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gpu.cpp
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gpu.h
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@ -16,6 +16,7 @@
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_compute.h"
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#include "video_core/engines/maxwell_dma.h"
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#include "video_core/gpu.h"
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#include "video_core/renderer_base.h"
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#include "video_core/video_core.h"
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@ -60,8 +61,11 @@ void GPU::WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params)
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case EngineID::MAXWELL_COMPUTE_B:
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maxwell_compute->WriteReg(method, value);
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break;
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case EngineID::MAXWELL_DMA_COPY_A:
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maxwell_dma->WriteReg(method, value);
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break;
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default:
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UNIMPLEMENTED();
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UNIMPLEMENTED_MSG("Unimplemented engine");
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}
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}
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@ -47,6 +47,7 @@ void Fermi2D::HandleSurfaceCopy() {
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if (regs.src.linear == regs.dst.linear) {
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// If the input layout and the output layout are the same, just perform a raw copy.
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ASSERT(regs.src.BlockHeight() == regs.dst.BlockHeight());
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Memory::CopyBlock(dest_cpu, source_cpu,
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src_bytes_per_pixel * regs.dst.width * regs.dst.height);
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return;
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69
src/video_core/engines/maxwell_dma.cpp
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69
src/video_core/engines/maxwell_dma.cpp
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@ -0,0 +1,69 @@
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "core/memory.h"
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#include "video_core/engines/maxwell_dma.h"
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#include "video_core/textures/decoders.h"
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namespace Tegra {
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namespace Engines {
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MaxwellDMA::MaxwellDMA(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
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void MaxwellDMA::WriteReg(u32 method, u32 value) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid MaxwellDMA register, increase the size of the Regs structure");
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regs.reg_array[method] = value;
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#define MAXWELLDMA_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::MaxwellDMA::Regs, field_name) / sizeof(u32))
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switch (method) {
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case MAXWELLDMA_REG_INDEX(exec): {
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HandleCopy();
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break;
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}
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}
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#undef MAXWELLDMA_REG_INDEX
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}
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void MaxwellDMA::HandleCopy() {
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NGLOG_WARNING(HW_GPU, "Requested a DMA copy");
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const GPUVAddr source = regs.src_address.Address();
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const GPUVAddr dest = regs.dst_address.Address();
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const VAddr source_cpu = *memory_manager.GpuToCpuAddress(source);
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const VAddr dest_cpu = *memory_manager.GpuToCpuAddress(dest);
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// TODO(Subv): Perform more research and implement all features of this engine.
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ASSERT(regs.exec.enable_swizzle == 0);
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ASSERT(regs.exec.enable_2d == 1);
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ASSERT(regs.exec.query_mode == Regs::QueryMode::None);
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ASSERT(regs.exec.query_intr == Regs::QueryIntr::None);
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ASSERT(regs.exec.copy_mode == Regs::CopyMode::Unk2);
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ASSERT(regs.src_params.pos_x == 0);
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ASSERT(regs.src_params.pos_y == 0);
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ASSERT(regs.dst_params.pos_x == 0);
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ASSERT(regs.dst_params.pos_y == 0);
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ASSERT(regs.exec.is_dst_linear != regs.exec.is_src_linear);
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u8* src_buffer = Memory::GetPointer(source_cpu);
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u8* dst_buffer = Memory::GetPointer(dest_cpu);
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if (regs.exec.is_dst_linear && !regs.exec.is_src_linear) {
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// If the input is tiled and the output is linear, deswizzle the input and copy it over.
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Texture::CopySwizzledData(regs.src_params.size_x, regs.src_params.size_y, 1, 1, src_buffer,
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dst_buffer, true, regs.src_params.BlockHeight());
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} else {
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// If the input is linear and the output is tiled, swizzle the input and copy it over.
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Texture::CopySwizzledData(regs.dst_params.size_x, regs.dst_params.size_y, 1, 1, dst_buffer,
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src_buffer, false, regs.dst_params.BlockHeight());
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}
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}
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} // namespace Engines
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} // namespace Tegra
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155
src/video_core/engines/maxwell_dma.h
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155
src/video_core/engines/maxwell_dma.h
Normal file
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@ -0,0 +1,155 @@
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/gpu.h"
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#include "video_core/memory_manager.h"
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namespace Tegra {
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namespace Engines {
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class MaxwellDMA final {
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public:
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explicit MaxwellDMA(MemoryManager& memory_manager);
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~MaxwellDMA() = default;
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value);
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struct Regs {
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static constexpr size_t NUM_REGS = 0x1D6;
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struct Parameters {
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union {
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BitField<0, 4, u32> block_depth;
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BitField<4, 4, u32> block_height;
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BitField<8, 4, u32> block_width;
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};
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u32 size_x;
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u32 size_y;
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u32 size_z;
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u32 pos_z;
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union {
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BitField<0, 16, u32> pos_x;
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BitField<16, 16, u32> pos_y;
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};
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u32 BlockHeight() const {
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return 1 << block_height;
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}
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};
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static_assert(sizeof(Parameters) == 24, "Parameters has wrong size");
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enum class CopyMode : u32 {
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None = 0,
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Unk1 = 1,
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Unk2 = 2,
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};
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enum class QueryMode : u32 {
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None = 0,
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Short = 1,
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Long = 2,
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};
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enum class QueryIntr : u32 {
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None = 0,
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Block = 1,
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NonBlock = 2,
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};
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union {
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struct {
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INSERT_PADDING_WORDS(0xC0);
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struct {
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union {
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BitField<0, 2, CopyMode> copy_mode;
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BitField<2, 1, u32> flush;
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BitField<3, 2, QueryMode> query_mode;
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BitField<5, 2, QueryIntr> query_intr;
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BitField<7, 1, u32> is_src_linear;
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BitField<8, 1, u32> is_dst_linear;
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BitField<9, 1, u32> enable_2d;
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BitField<10, 1, u32> enable_swizzle;
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};
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} exec;
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INSERT_PADDING_WORDS(0x3F);
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struct {
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u32 address_high;
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u32 address_low;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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} src_address;
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struct {
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u32 address_high;
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u32 address_low;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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} dst_address;
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u32 src_pitch;
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u32 dst_pitch;
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u32 x_count;
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u32 y_count;
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INSERT_PADDING_WORDS(0xBB);
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Parameters dst_params;
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INSERT_PADDING_WORDS(1);
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Parameters src_params;
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INSERT_PADDING_WORDS(0x13);
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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MemoryManager& memory_manager;
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private:
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/// Performs the copy from the source buffer to the destination buffer as configured in the
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/// registers.
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void HandleCopy();
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(MaxwellDMA::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(exec, 0xC0);
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ASSERT_REG_POSITION(src_address, 0x100);
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ASSERT_REG_POSITION(dst_address, 0x102);
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ASSERT_REG_POSITION(src_pitch, 0x104);
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ASSERT_REG_POSITION(dst_pitch, 0x105);
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ASSERT_REG_POSITION(x_count, 0x106);
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ASSERT_REG_POSITION(y_count, 0x107);
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ASSERT_REG_POSITION(dst_params, 0x1C3);
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ASSERT_REG_POSITION(src_params, 0x1CA);
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#undef ASSERT_REG_POSITION
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} // namespace Engines
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} // namespace Tegra
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@ -5,6 +5,7 @@
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_compute.h"
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#include "video_core/engines/maxwell_dma.h"
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#include "video_core/gpu.h"
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namespace Tegra {
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@ -14,6 +15,7 @@ GPU::GPU() {
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maxwell_3d = std::make_unique<Engines::Maxwell3D>(*memory_manager);
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fermi_2d = std::make_unique<Engines::Fermi2D>(*memory_manager);
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maxwell_compute = std::make_unique<Engines::MaxwellCompute>();
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maxwell_dma = std::make_unique<Engines::MaxwellDMA>(*memory_manager);
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}
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GPU::~GPU() = default;
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@ -63,6 +63,7 @@ namespace Engines {
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class Fermi2D;
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class Maxwell3D;
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class MaxwellCompute;
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class MaxwellDMA;
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} // namespace Engines
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enum class EngineID {
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std::unique_ptr<Engines::Fermi2D> fermi_2d;
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/// Compute engine
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std::unique_ptr<Engines::MaxwellCompute> maxwell_compute;
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/// DMA engine
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std::unique_ptr<Engines::MaxwellDMA> maxwell_dma;
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};
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} // namespace Tegra
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