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Merge pull request #553 from Subv/iset
GPU: Implement the ISET family of shader instructions.
This commit is contained in:
commit
281fd881a0
2 changed files with 53 additions and 2 deletions
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@ -329,6 +329,15 @@ union Instruction {
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BitField<56, 1, u64> neg_imm;
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} fset;
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union {
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BitField<39, 3, u64> pred39;
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BitField<42, 1, u64> neg_pred;
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BitField<44, 1, u64> bf;
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BitField<45, 2, PredOperation> op;
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BitField<48, 1, u64> is_signed;
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BitField<49, 3, PredCondition> cond;
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} iset;
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union {
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BitField<10, 2, Register::Size> size;
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BitField<12, 1, u64> is_output_signed;
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@ -487,6 +496,9 @@ public:
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ISETP_C,
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ISETP_IMM,
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ISETP_R,
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ISET_R,
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ISET_C,
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ISET_IMM,
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PSETP,
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XMAD_IMM,
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XMAD_CR,
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@ -506,6 +518,7 @@ public:
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Memory,
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FloatSet,
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FloatSetPredicate,
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IntegerSet,
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IntegerSetPredicate,
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PredicateSetPredicate,
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Conversion,
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@ -677,6 +690,9 @@ private:
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INST("010010110110----", Id::ISETP_C, Type::IntegerSetPredicate, "ISETP_C"),
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INST("010110110110----", Id::ISETP_R, Type::IntegerSetPredicate, "ISETP_R"),
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INST("0011011-0110----", Id::ISETP_IMM, Type::IntegerSetPredicate, "ISETP_IMM"),
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INST("010110110101----", Id::ISET_R, Type::IntegerSet, "ISET_R"),
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INST("010010110101----", Id::ISET_C, Type::IntegerSet, "ISET_C"),
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INST("0011011-0101----", Id::ISET_IMM, Type::IntegerSet, "ISET_IMM"),
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INST("0101000010010---", Id::PSETP, Type::PredicateSetPredicate, "PSETP"),
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INST("0011011-00------", Id::XMAD_IMM, Type::Arithmetic, "XMAD_IMM"),
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INST("0100111---------", Id::XMAD_CR, Type::Arithmetic, "XMAD_CR"),
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@ -1423,8 +1423,8 @@ private:
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op_b = "abs(" + op_b + ')';
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}
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// The fset instruction sets a register to 1.0 if the condition is true, and to 0
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// otherwise.
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// The fset instruction sets a register to 1.0 or -1 (depending on the bf bit) if the
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// condition is true, and to 0 otherwise.
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std::string second_pred =
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GetPredicateCondition(instr.fset.pred39, instr.fset.neg_pred != 0);
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@ -1442,6 +1442,41 @@ private:
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}
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break;
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}
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case OpCode::Type::IntegerSet: {
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std::string op_a = regs.GetRegisterAsInteger(instr.gpr8, 0, instr.iset.is_signed);
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std::string op_b;
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if (instr.is_b_imm) {
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op_b = std::to_string(instr.alu.GetSignedImm20_20());
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} else {
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if (instr.is_b_gpr) {
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op_b = regs.GetRegisterAsInteger(instr.gpr20, 0, instr.iset.is_signed);
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} else {
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op_b = regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
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GLSLRegister::Type::Integer);
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}
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}
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// The iset instruction sets a register to 1.0 or -1 (depending on the bf bit) if the
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// condition is true, and to 0 otherwise.
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std::string second_pred =
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GetPredicateCondition(instr.iset.pred39, instr.iset.neg_pred != 0);
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std::string comparator = GetPredicateComparison(instr.iset.cond);
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std::string combiner = GetPredicateCombiner(instr.iset.op);
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std::string predicate = "(((" + op_a + ") " + comparator + " (" + op_b + ")) " +
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combiner + " (" + second_pred + "))";
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if (instr.iset.bf) {
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regs.SetRegisterToFloat(instr.gpr0, 0, predicate + " ? 1.0 : 0.0", 1, 1);
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} else {
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regs.SetRegisterToInteger(instr.gpr0, false, 0, predicate + " ? 0xFFFFFFFF : 0", 1,
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1);
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}
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break;
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}
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default: {
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switch (opcode->GetId()) {
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case OpCode::Id::EXIT: {
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