418 lines
16 KiB
C++
418 lines
16 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include <list>
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#include <map>
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#include <optional>
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#include <set>
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#include <tuple>
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#include <vector>
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#include "common/common_types.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/engines/shader_header.h"
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#include "video_core/shader/ast.h"
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#include "video_core/shader/compiler_settings.h"
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#include "video_core/shader/const_buffer_locker.h"
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#include "video_core/shader/node.h"
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namespace VideoCommon::Shader {
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struct ShaderBlock;
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using ProgramCode = std::vector<u64>;
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constexpr u32 MAX_PROGRAM_LENGTH = 0x1000;
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class ConstBuffer {
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public:
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explicit ConstBuffer(u32 max_offset, bool is_indirect)
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: max_offset{max_offset}, is_indirect{is_indirect} {}
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ConstBuffer() = default;
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void MarkAsUsed(u64 offset) {
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max_offset = std::max(max_offset, static_cast<u32>(offset));
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}
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void MarkAsUsedIndirect() {
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is_indirect = true;
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}
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bool IsIndirect() const {
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return is_indirect;
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}
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u32 GetSize() const {
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return max_offset + sizeof(float);
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}
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u32 GetMaxOffset() const {
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return max_offset;
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}
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private:
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u32 max_offset{};
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bool is_indirect{};
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};
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struct GlobalMemoryUsage {
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bool is_read{};
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bool is_written{};
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};
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class ShaderIR final {
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public:
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explicit ShaderIR(const ProgramCode& program_code, u32 main_offset, CompilerSettings settings,
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ConstBufferLocker& locker);
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~ShaderIR();
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const std::map<u32, NodeBlock>& GetBasicBlocks() const {
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return basic_blocks;
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}
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const std::set<u32>& GetRegisters() const {
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return used_registers;
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}
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const std::set<Tegra::Shader::Pred>& GetPredicates() const {
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return used_predicates;
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}
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const std::set<Tegra::Shader::Attribute::Index>& GetInputAttributes() const {
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return used_input_attributes;
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}
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const std::set<Tegra::Shader::Attribute::Index>& GetOutputAttributes() const {
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return used_output_attributes;
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}
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const std::map<u32, ConstBuffer>& GetConstantBuffers() const {
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return used_cbufs;
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}
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const std::list<Sampler>& GetSamplers() const {
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return used_samplers;
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}
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const std::list<Image>& GetImages() const {
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return used_images;
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}
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const std::array<bool, Tegra::Engines::Maxwell3D::Regs::NumClipDistances>& GetClipDistances()
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const {
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return used_clip_distances;
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}
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const std::map<GlobalMemoryBase, GlobalMemoryUsage>& GetGlobalMemory() const {
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return used_global_memory;
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}
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std::size_t GetLength() const {
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return static_cast<std::size_t>(coverage_end * sizeof(u64));
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}
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bool UsesLayer() const {
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return uses_layer;
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}
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bool UsesViewportIndex() const {
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return uses_viewport_index;
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}
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bool UsesPointSize() const {
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return uses_point_size;
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}
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bool UsesInstanceId() const {
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return uses_instance_id;
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}
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bool UsesVertexId() const {
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return uses_vertex_id;
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}
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bool HasPhysicalAttributes() const {
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return uses_physical_attributes;
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}
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const Tegra::Shader::Header& GetHeader() const {
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return header;
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}
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bool IsFlowStackDisabled() const {
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return disable_flow_stack;
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}
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bool IsDecompiled() const {
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return decompiled;
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}
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const ASTManager& GetASTManager() const {
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return program_manager;
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}
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ASTNode GetASTProgram() const {
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return program_manager.GetProgram();
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}
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u32 GetASTNumVariables() const {
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return program_manager.GetVariables();
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}
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u32 ConvertAddressToNvidiaSpace(const u32 address) const {
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return (address - main_offset) * sizeof(Tegra::Shader::Instruction);
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}
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/// Returns a condition code evaluated from internal flags
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Node GetConditionCode(Tegra::Shader::ConditionCode cc) const;
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private:
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friend class ASTDecoder;
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struct SamplerInfo {
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Tegra::Shader::TextureType type;
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bool is_array;
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bool is_shadow;
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};
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void Decode();
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NodeBlock DecodeRange(u32 begin, u32 end);
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void DecodeRangeInner(NodeBlock& bb, u32 begin, u32 end);
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void InsertControlFlow(NodeBlock& bb, const ShaderBlock& block);
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/**
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* Decodes a single instruction from Tegra to IR.
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* @param bb Basic block where the nodes will be written to.
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* @param pc Program counter. Offset to decode.
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* @return Next address to decode.
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*/
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u32 DecodeInstr(NodeBlock& bb, u32 pc);
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u32 DecodeArithmetic(NodeBlock& bb, u32 pc);
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u32 DecodeArithmeticImmediate(NodeBlock& bb, u32 pc);
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u32 DecodeBfe(NodeBlock& bb, u32 pc);
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u32 DecodeBfi(NodeBlock& bb, u32 pc);
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u32 DecodeShift(NodeBlock& bb, u32 pc);
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u32 DecodeArithmeticInteger(NodeBlock& bb, u32 pc);
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u32 DecodeArithmeticIntegerImmediate(NodeBlock& bb, u32 pc);
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u32 DecodeArithmeticHalf(NodeBlock& bb, u32 pc);
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u32 DecodeArithmeticHalfImmediate(NodeBlock& bb, u32 pc);
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u32 DecodeFfma(NodeBlock& bb, u32 pc);
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u32 DecodeHfma2(NodeBlock& bb, u32 pc);
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u32 DecodeConversion(NodeBlock& bb, u32 pc);
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u32 DecodeWarp(NodeBlock& bb, u32 pc);
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u32 DecodeMemory(NodeBlock& bb, u32 pc);
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u32 DecodeTexture(NodeBlock& bb, u32 pc);
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u32 DecodeImage(NodeBlock& bb, u32 pc);
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u32 DecodeFloatSetPredicate(NodeBlock& bb, u32 pc);
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u32 DecodeIntegerSetPredicate(NodeBlock& bb, u32 pc);
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u32 DecodeHalfSetPredicate(NodeBlock& bb, u32 pc);
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u32 DecodePredicateSetRegister(NodeBlock& bb, u32 pc);
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u32 DecodePredicateSetPredicate(NodeBlock& bb, u32 pc);
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u32 DecodeRegisterSetPredicate(NodeBlock& bb, u32 pc);
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u32 DecodeFloatSet(NodeBlock& bb, u32 pc);
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u32 DecodeIntegerSet(NodeBlock& bb, u32 pc);
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u32 DecodeHalfSet(NodeBlock& bb, u32 pc);
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u32 DecodeVideo(NodeBlock& bb, u32 pc);
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u32 DecodeXmad(NodeBlock& bb, u32 pc);
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u32 DecodeOther(NodeBlock& bb, u32 pc);
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/// Generates a node for a passed register.
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Node GetRegister(Tegra::Shader::Register reg);
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/// Generates a node representing a 19-bit immediate value
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Node GetImmediate19(Tegra::Shader::Instruction instr);
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/// Generates a node representing a 32-bit immediate value
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Node GetImmediate32(Tegra::Shader::Instruction instr);
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/// Generates a node representing a constant buffer
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Node GetConstBuffer(u64 index, u64 offset);
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/// Generates a node representing a constant buffer with a variadic offset
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Node GetConstBufferIndirect(u64 index, u64 offset, Node node);
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/// Generates a node for a passed predicate. It can be optionally negated
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Node GetPredicate(u64 pred, bool negated = false);
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/// Generates a predicate node for an immediate true or false value
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Node GetPredicate(bool immediate);
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/// Generates a node representing an input attribute. Keeps track of used attributes.
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Node GetInputAttribute(Tegra::Shader::Attribute::Index index, u64 element, Node buffer = {});
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/// Generates a node representing a physical input attribute.
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Node GetPhysicalInputAttribute(Tegra::Shader::Register physical_address, Node buffer = {});
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/// Generates a node representing an output attribute. Keeps track of used attributes.
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Node GetOutputAttribute(Tegra::Shader::Attribute::Index index, u64 element, Node buffer);
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/// Generates a node representing an internal flag
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Node GetInternalFlag(InternalFlag flag, bool negated = false) const;
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/// Generates a node representing a local memory address
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Node GetLocalMemory(Node address);
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/// Generates a node representing a shared memory address
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Node GetSharedMemory(Node address);
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/// Generates a temporary, internally it uses a post-RZ register
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Node GetTemporary(u32 id);
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/// Sets a register. src value must be a number-evaluated node.
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void SetRegister(NodeBlock& bb, Tegra::Shader::Register dest, Node src);
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/// Sets a predicate. src value must be a bool-evaluated node
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void SetPredicate(NodeBlock& bb, u64 dest, Node src);
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/// Sets an internal flag. src value must be a bool-evaluated node
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void SetInternalFlag(NodeBlock& bb, InternalFlag flag, Node value);
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/// Sets a local memory address with a value.
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void SetLocalMemory(NodeBlock& bb, Node address, Node value);
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/// Sets a shared memory address with a value.
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void SetSharedMemory(NodeBlock& bb, Node address, Node value);
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/// Sets a temporary. Internally it uses a post-RZ register
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void SetTemporary(NodeBlock& bb, u32 id, Node value);
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/// Sets internal flags from a float
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void SetInternalFlagsFromFloat(NodeBlock& bb, Node value, bool sets_cc = true);
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/// Sets internal flags from an integer
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void SetInternalFlagsFromInteger(NodeBlock& bb, Node value, bool sets_cc = true);
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/// Conditionally absolute/negated float. Absolute is applied first
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Node GetOperandAbsNegFloat(Node value, bool absolute, bool negate);
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/// Conditionally saturates a float
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Node GetSaturatedFloat(Node value, bool saturate = true);
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/// Converts an integer to different sizes.
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Node ConvertIntegerSize(Node value, Tegra::Shader::Register::Size size, bool is_signed);
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/// Conditionally absolute/negated integer. Absolute is applied first
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Node GetOperandAbsNegInteger(Node value, bool absolute, bool negate, bool is_signed);
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/// Unpacks a half immediate from an instruction
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Node UnpackHalfImmediate(Tegra::Shader::Instruction instr, bool has_negation);
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/// Unpacks a binary value into a half float pair with a type format
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Node UnpackHalfFloat(Node value, Tegra::Shader::HalfType type);
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/// Merges a half pair into another value
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Node HalfMerge(Node dest, Node src, Tegra::Shader::HalfMerge merge);
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/// Conditionally absolute/negated half float pair. Absolute is applied first
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Node GetOperandAbsNegHalf(Node value, bool absolute, bool negate);
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/// Conditionally saturates a half float pair
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Node GetSaturatedHalfFloat(Node value, bool saturate = true);
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/// Returns a predicate comparing two floats
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Node GetPredicateComparisonFloat(Tegra::Shader::PredCondition condition, Node op_a, Node op_b);
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/// Returns a predicate comparing two integers
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Node GetPredicateComparisonInteger(Tegra::Shader::PredCondition condition, bool is_signed,
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Node op_a, Node op_b);
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/// Returns a predicate comparing two half floats. meta consumes how both pairs will be compared
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Node GetPredicateComparisonHalf(Tegra::Shader::PredCondition condition, Node op_a, Node op_b);
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/// Returns a predicate combiner operation
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OperationCode GetPredicateCombiner(Tegra::Shader::PredOperation operation);
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/// Accesses a texture sampler
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const Sampler& GetSampler(const Tegra::Shader::Sampler& sampler,
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std::optional<SamplerInfo> sampler_info);
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// Accesses a texture sampler for a bindless texture.
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const Sampler& GetBindlessSampler(const Tegra::Shader::Register& reg,
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std::optional<SamplerInfo> sampler_info);
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/// Accesses an image.
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Image& GetImage(Tegra::Shader::Image image, Tegra::Shader::ImageType type);
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/// Access a bindless image sampler.
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Image& GetBindlessImage(Tegra::Shader::Register reg, Tegra::Shader::ImageType type);
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/// Extracts a sequence of bits from a node
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Node BitfieldExtract(Node value, u32 offset, u32 bits);
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/// Inserts a sequence of bits from a node
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Node BitfieldInsert(Node base, Node insert, u32 offset, u32 bits);
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void WriteTexInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
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const Node4& components);
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void WriteTexsInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
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const Node4& components, bool ignore_mask = false);
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void WriteTexsInstructionHalfFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
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const Node4& components);
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Node4 GetTexCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
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bool is_array, bool is_aoffi,
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std::optional<Tegra::Shader::Register> bindless_reg);
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Node4 GetTexsCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
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bool is_array);
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Node4 GetTld4Code(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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bool depth_compare, bool is_array, bool is_aoffi, bool is_bindless);
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Node4 GetTldCode(Tegra::Shader::Instruction instr);
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Node4 GetTldsCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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bool is_array);
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std::tuple<std::size_t, std::size_t> ValidateAndGetCoordinateElement(
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Tegra::Shader::TextureType texture_type, bool depth_compare, bool is_array,
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bool lod_bias_enabled, std::size_t max_coords, std::size_t max_inputs);
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std::vector<Node> GetAoffiCoordinates(Node aoffi_reg, std::size_t coord_count, bool is_tld4);
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Node4 GetTextureCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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Tegra::Shader::TextureProcessMode process_mode, std::vector<Node> coords,
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Node array, Node depth_compare, u32 bias_offset, std::vector<Node> aoffi,
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std::optional<Tegra::Shader::Register> bindless_reg);
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Node GetVideoOperand(Node op, bool is_chunk, bool is_signed, Tegra::Shader::VideoType type,
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u64 byte_height);
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void WriteLogicOperation(NodeBlock& bb, Tegra::Shader::Register dest,
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Tegra::Shader::LogicOperation logic_op, Node op_a, Node op_b,
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Tegra::Shader::PredicateResultMode predicate_mode,
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Tegra::Shader::Pred predicate, bool sets_cc);
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void WriteLop3Instruction(NodeBlock& bb, Tegra::Shader::Register dest, Node op_a, Node op_b,
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Node op_c, Node imm_lut, bool sets_cc);
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std::tuple<Node, u32, u32> TrackCbuf(Node tracked, const NodeBlock& code, s64 cursor) const;
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std::optional<u32> TrackImmediate(Node tracked, const NodeBlock& code, s64 cursor) const;
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std::pair<Node, s64> TrackRegister(const GprNode* tracked, const NodeBlock& code,
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s64 cursor) const;
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std::tuple<Node, Node, GlobalMemoryBase> TrackGlobalMemory(NodeBlock& bb,
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Tegra::Shader::Instruction instr,
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bool is_write);
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const ProgramCode& program_code;
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const u32 main_offset;
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const CompilerSettings settings;
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ConstBufferLocker& locker;
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bool decompiled{};
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bool disable_flow_stack{};
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u32 coverage_begin{};
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u32 coverage_end{};
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std::map<u32, NodeBlock> basic_blocks;
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NodeBlock global_code;
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ASTManager program_manager{true, true};
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std::set<u32> used_registers;
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std::set<Tegra::Shader::Pred> used_predicates;
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std::set<Tegra::Shader::Attribute::Index> used_input_attributes;
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std::set<Tegra::Shader::Attribute::Index> used_output_attributes;
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std::map<u32, ConstBuffer> used_cbufs;
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std::list<Sampler> used_samplers;
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std::list<Image> used_images;
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std::array<bool, Tegra::Engines::Maxwell3D::Regs::NumClipDistances> used_clip_distances{};
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std::map<GlobalMemoryBase, GlobalMemoryUsage> used_global_memory;
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bool uses_layer{};
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bool uses_viewport_index{};
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bool uses_point_size{};
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bool uses_physical_attributes{}; // Shader uses AL2P or physical attribute read/writes
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bool uses_instance_id{};
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bool uses_vertex_id{};
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Tegra::Shader::Header header;
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};
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} // namespace VideoCommon::Shader
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