276 lines
11 KiB
C++
276 lines
11 KiB
C++
// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <bit>
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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#include "shader_recompiler/backend/spirv/emit_spirv_instructions.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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Id StorageIndex(EmitContext& ctx, const IR::Value& offset, size_t element_size,
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u32 index_offset = 0) {
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if (offset.IsImmediate()) {
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const u32 imm_offset{static_cast<u32>(offset.U32() / element_size) + index_offset};
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return ctx.Const(imm_offset);
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}
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const u32 shift{static_cast<u32>(std::countr_zero(element_size))};
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Id index{ctx.Def(offset)};
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if (shift != 0) {
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const Id shift_id{ctx.Const(shift)};
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index = ctx.OpShiftRightLogical(ctx.U32[1], index, shift_id);
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}
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if (index_offset != 0) {
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index = ctx.OpIAdd(ctx.U32[1], index, ctx.Const(index_offset));
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}
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return index;
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}
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Id StoragePointer(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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const StorageTypeDefinition& type_def, size_t element_size,
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Id StorageDefinitions::*member_ptr, u32 index_offset = 0) {
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if (!binding.IsImmediate()) {
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throw NotImplementedException("Dynamic storage buffer indexing");
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}
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const Id ssbo{ctx.ssbos[binding.U32()].*member_ptr};
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const Id index{StorageIndex(ctx, offset, element_size, index_offset)};
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return ctx.OpAccessChain(type_def.element, ssbo, ctx.u32_zero_value, index);
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}
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Id LoadStorage(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, Id result_type,
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const StorageTypeDefinition& type_def, size_t element_size,
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Id StorageDefinitions::*member_ptr, u32 index_offset = 0) {
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const Id pointer{
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StoragePointer(ctx, binding, offset, type_def, element_size, member_ptr, index_offset)};
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return ctx.OpLoad(result_type, pointer);
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}
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Id LoadStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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u32 index_offset = 0) {
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return LoadStorage(ctx, binding, offset, ctx.U32[1], ctx.storage_types.U32, sizeof(u32),
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&StorageDefinitions::U32, index_offset);
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}
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void WriteStorage(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, Id value,
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const StorageTypeDefinition& type_def, size_t element_size,
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Id StorageDefinitions::*member_ptr, u32 index_offset = 0) {
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const Id pointer{
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StoragePointer(ctx, binding, offset, type_def, element_size, member_ptr, index_offset)};
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ctx.OpStore(pointer, value);
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}
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void WriteStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, Id value,
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u32 index_offset = 0) {
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WriteStorage(ctx, binding, offset, value, ctx.storage_types.U32, sizeof(u32),
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&StorageDefinitions::U32, index_offset);
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}
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} // Anonymous namespace
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void EmitLoadGlobalU8(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitLoadGlobalS8(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitLoadGlobalU16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitLoadGlobalS16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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Id EmitLoadGlobal32(EmitContext& ctx, Id address) {
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if (ctx.profile.support_int64) {
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return ctx.OpFunctionCall(ctx.U32[1], ctx.load_global_func_u32, address);
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}
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LOG_WARNING(Shader_SPIRV, "Int64 not supported, ignoring memory operation");
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return ctx.Const(0u);
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}
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Id EmitLoadGlobal64(EmitContext& ctx, Id address) {
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if (ctx.profile.support_int64) {
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return ctx.OpFunctionCall(ctx.U32[2], ctx.load_global_func_u32x2, address);
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}
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LOG_WARNING(Shader_SPIRV, "Int64 not supported, ignoring memory operation");
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return ctx.Const(0u, 0u);
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}
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Id EmitLoadGlobal128(EmitContext& ctx, Id address) {
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if (ctx.profile.support_int64) {
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return ctx.OpFunctionCall(ctx.U32[4], ctx.load_global_func_u32x4, address);
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}
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LOG_WARNING(Shader_SPIRV, "Int64 not supported, ignoring memory operation");
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return ctx.Const(0u, 0u, 0u, 0u);
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}
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void EmitWriteGlobalU8(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteGlobalS8(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteGlobalU16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteGlobalS16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteGlobal32(EmitContext& ctx, Id address, Id value) {
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if (ctx.profile.support_int64) {
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ctx.OpFunctionCall(ctx.void_id, ctx.write_global_func_u32, address, value);
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return;
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}
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LOG_WARNING(Shader_SPIRV, "Int64 not supported, ignoring memory operation");
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}
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void EmitWriteGlobal64(EmitContext& ctx, Id address, Id value) {
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if (ctx.profile.support_int64) {
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ctx.OpFunctionCall(ctx.void_id, ctx.write_global_func_u32x2, address, value);
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return;
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}
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LOG_WARNING(Shader_SPIRV, "Int64 not supported, ignoring memory operation");
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}
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void EmitWriteGlobal128(EmitContext& ctx, Id address, Id value) {
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if (ctx.profile.support_int64) {
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ctx.OpFunctionCall(ctx.void_id, ctx.write_global_func_u32x4, address, value);
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return;
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}
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LOG_WARNING(Shader_SPIRV, "Int64 not supported, ignoring memory operation");
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}
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Id EmitLoadStorageU8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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if (ctx.profile.support_int8 && ctx.profile.support_descriptor_aliasing) {
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return ctx.OpUConvert(ctx.U32[1],
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LoadStorage(ctx, binding, offset, ctx.U8, ctx.storage_types.U8,
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sizeof(u8), &StorageDefinitions::U8));
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} else {
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return ctx.OpBitFieldUExtract(ctx.U32[1], LoadStorage32(ctx, binding, offset),
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ctx.BitOffset8(offset), ctx.Const(8u));
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}
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}
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Id EmitLoadStorageS8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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if (ctx.profile.support_int8 && ctx.profile.support_descriptor_aliasing) {
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return ctx.OpSConvert(ctx.U32[1],
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LoadStorage(ctx, binding, offset, ctx.S8, ctx.storage_types.S8,
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sizeof(s8), &StorageDefinitions::S8));
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} else {
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return ctx.OpBitFieldSExtract(ctx.U32[1], LoadStorage32(ctx, binding, offset),
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ctx.BitOffset8(offset), ctx.Const(8u));
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}
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}
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Id EmitLoadStorageU16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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if (ctx.profile.support_int16 && ctx.profile.support_descriptor_aliasing) {
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return ctx.OpUConvert(ctx.U32[1],
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LoadStorage(ctx, binding, offset, ctx.U16, ctx.storage_types.U16,
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sizeof(u16), &StorageDefinitions::U16));
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} else {
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return ctx.OpBitFieldUExtract(ctx.U32[1], LoadStorage32(ctx, binding, offset),
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ctx.BitOffset16(offset), ctx.Const(16u));
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}
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}
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Id EmitLoadStorageS16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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if (ctx.profile.support_int16 && ctx.profile.support_descriptor_aliasing) {
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return ctx.OpSConvert(ctx.U32[1],
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LoadStorage(ctx, binding, offset, ctx.S16, ctx.storage_types.S16,
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sizeof(s16), &StorageDefinitions::S16));
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} else {
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return ctx.OpBitFieldSExtract(ctx.U32[1], LoadStorage32(ctx, binding, offset),
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ctx.BitOffset16(offset), ctx.Const(16u));
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}
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}
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Id EmitLoadStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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return LoadStorage32(ctx, binding, offset);
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}
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Id EmitLoadStorage64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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if (ctx.profile.support_descriptor_aliasing) {
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return LoadStorage(ctx, binding, offset, ctx.U32[2], ctx.storage_types.U32x2,
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sizeof(u32[2]), &StorageDefinitions::U32x2);
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} else {
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return ctx.OpCompositeConstruct(ctx.U32[2], LoadStorage32(ctx, binding, offset, 0),
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LoadStorage32(ctx, binding, offset, 1));
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}
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}
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Id EmitLoadStorage128(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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if (ctx.profile.support_descriptor_aliasing) {
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return LoadStorage(ctx, binding, offset, ctx.U32[4], ctx.storage_types.U32x4,
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sizeof(u32[4]), &StorageDefinitions::U32x4);
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} else {
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return ctx.OpCompositeConstruct(ctx.U32[4], LoadStorage32(ctx, binding, offset, 0),
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LoadStorage32(ctx, binding, offset, 1),
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LoadStorage32(ctx, binding, offset, 2),
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LoadStorage32(ctx, binding, offset, 3));
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}
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}
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void EmitWriteStorageU8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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WriteStorage(ctx, binding, offset, ctx.OpSConvert(ctx.U8, value), ctx.storage_types.U8,
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sizeof(u8), &StorageDefinitions::U8);
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}
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void EmitWriteStorageS8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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WriteStorage(ctx, binding, offset, ctx.OpSConvert(ctx.S8, value), ctx.storage_types.S8,
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sizeof(s8), &StorageDefinitions::S8);
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}
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void EmitWriteStorageU16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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WriteStorage(ctx, binding, offset, ctx.OpSConvert(ctx.U16, value), ctx.storage_types.U16,
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sizeof(u16), &StorageDefinitions::U16);
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}
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void EmitWriteStorageS16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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WriteStorage(ctx, binding, offset, ctx.OpSConvert(ctx.S16, value), ctx.storage_types.S16,
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sizeof(s16), &StorageDefinitions::S16);
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}
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void EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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WriteStorage32(ctx, binding, offset, value);
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}
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void EmitWriteStorage64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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if (ctx.profile.support_descriptor_aliasing) {
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WriteStorage(ctx, binding, offset, value, ctx.storage_types.U32x2, sizeof(u32[2]),
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&StorageDefinitions::U32x2);
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} else {
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for (u32 index = 0; index < 2; ++index) {
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const Id element{ctx.OpCompositeExtract(ctx.U32[1], value, index)};
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WriteStorage32(ctx, binding, offset, element, index);
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}
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}
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}
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void EmitWriteStorage128(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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if (ctx.profile.support_descriptor_aliasing) {
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WriteStorage(ctx, binding, offset, value, ctx.storage_types.U32x4, sizeof(u32[4]),
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&StorageDefinitions::U32x4);
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} else {
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for (u32 index = 0; index < 4; ++index) {
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const Id element{ctx.OpCompositeExtract(ctx.U32[1], value, index)};
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WriteStorage32(ctx, binding, offset, element, index);
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}
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}
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}
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} // namespace Shader::Backend::SPIRV
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