18a5e888bb
It's not really known how this actually works. Some testing has shown that this probably performs no filtering, and common usage in games suggests it's not actually resizing the image at all. However, this patch does seem to fix some homebrew showing quasi-duplicated images while still keeping other applications in a working state.
274 lines
11 KiB
C++
274 lines
11 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/common_types.h"
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#include "core/settings.h"
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#include "core/core.h"
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#include "core/mem_map.h"
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#include "core/hle/hle.h"
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#include "core/hle/service/gsp_gpu.h"
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#include "core/hw/gpu.h"
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#include "video_core/command_processor.h"
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#include "video_core/video_core.h"
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namespace GPU {
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Regs g_regs;
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bool g_skip_frame = false; ///< True if the current frame was skipped
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static u64 frame_ticks = 0; ///< 268MHz / gpu_refresh_rate frames per second
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static u64 line_ticks = 0; ///< Number of ticks for a screen line
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static u32 cur_line = 0; ///< Current screen line
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static u64 last_update_tick = 0; ///< CPU ticl count from last GPU update
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static u64 frame_count = 0; ///< Number of frames drawn
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static bool last_skip_frame = false; ///< True if the last frame was skipped
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template <typename T>
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inline void Read(T &var, const u32 raw_addr) {
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u32 addr = raw_addr - 0x1EF00000;
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u32 index = addr / 4;
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// Reads other than u32 are untested, so I'd rather have them abort than silently fail
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if (index >= Regs::NumIds() || !std::is_same<T, u32>::value) {
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LOG_ERROR(HW_GPU, "unknown Read%lu @ 0x%08X", sizeof(var) * 8, addr);
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return;
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}
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var = g_regs[addr / 4];
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}
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template <typename T>
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inline void Write(u32 addr, const T data) {
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addr -= 0x1EF00000;
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u32 index = addr / 4;
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// Writes other than u32 are untested, so I'd rather have them abort than silently fail
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if (index >= Regs::NumIds() || !std::is_same<T, u32>::value) {
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LOG_ERROR(HW_GPU, "unknown Write%lu 0x%08X @ 0x%08X", sizeof(data) * 8, (u32)data, addr);
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return;
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}
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g_regs[index] = static_cast<u32>(data);
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switch (index) {
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// Memory fills are triggered once the fill value is written.
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// NOTE: This is not verified.
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case GPU_REG_INDEX_WORKAROUND(memory_fill_config[0].value, 0x00004 + 0x3):
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case GPU_REG_INDEX_WORKAROUND(memory_fill_config[1].value, 0x00008 + 0x3):
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{
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const bool is_second_filler = (index != GPU_REG_INDEX(memory_fill_config[0].value));
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const auto& config = g_regs.memory_fill_config[is_second_filler];
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// TODO: Not sure if this check should be done at GSP level instead
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if (config.address_start) {
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// TODO: Not sure if this algorithm is correct, particularly because it doesn't use the size member at all
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u32* start = (u32*)Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetStartAddress()));
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u32* end = (u32*)Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetEndAddress()));
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for (u32* ptr = start; ptr < end; ++ptr)
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*ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation
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LOG_TRACE(HW_GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(), config.GetEndAddress());
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}
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break;
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}
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case GPU_REG_INDEX(display_transfer_config.trigger):
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{
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const auto& config = g_regs.display_transfer_config;
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if (config.trigger & 1) {
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u8* source_pointer = Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetPhysicalInputAddress()));
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u8* dest_pointer = Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetPhysicalOutputAddress()));
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for (u32 y = 0; y < config.output_height; ++y) {
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// TODO: Why does the register seem to hold twice the framebuffer width?
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for (u32 x = 0; x < config.output_width; ++x) {
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struct {
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int r, g, b, a;
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} source_color = { 0, 0, 0, 0 };
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// Cheap emulation of horizontal scaling: Just skip each second pixel of the
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// input framebuffer. We keep track of this in the pixel_skip variable.
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unsigned pixel_skip = (config.scale_horizontally != 0) ? 2 : 1;
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switch (config.input_format) {
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case Regs::PixelFormat::RGBA8:
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{
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// TODO: Most likely got the component order messed up.
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u8* srcptr = source_pointer + x * 4 * pixel_skip + y * config.input_width * 4 * pixel_skip;
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source_color.r = srcptr[0]; // blue
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source_color.g = srcptr[1]; // green
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source_color.b = srcptr[2]; // red
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source_color.a = srcptr[3]; // alpha
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break;
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}
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default:
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LOG_ERROR(HW_GPU, "Unknown source framebuffer format %x", config.input_format.Value());
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break;
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}
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switch (config.output_format) {
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/*case Regs::PixelFormat::RGBA8:
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{
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// TODO: Untested
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u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.output_width * 4);
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dstptr[0] = source_color.r;
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dstptr[1] = source_color.g;
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dstptr[2] = source_color.b;
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dstptr[3] = source_color.a;
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break;
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}*/
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case Regs::PixelFormat::RGB8:
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{
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// TODO: Most likely got the component order messed up.
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u8* dstptr = dest_pointer + x * 3 + y * config.output_width * 3;
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dstptr[0] = source_color.r; // blue
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dstptr[1] = source_color.g; // green
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dstptr[2] = source_color.b; // red
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break;
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}
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default:
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LOG_ERROR(HW_GPU, "Unknown destination framebuffer format %x", config.output_format.Value());
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break;
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}
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}
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}
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LOG_TRACE(HW_GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%ux%u)-> 0x%08x(%ux%u), dst format %x",
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config.output_height * config.output_width * 4,
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config.GetPhysicalInputAddress(), (u32)config.input_width, (u32)config.input_height,
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config.GetPhysicalOutputAddress(), (u32)config.output_width, (u32)config.output_height,
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config.output_format.Value());
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}
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break;
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}
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// Seems like writing to this register triggers processing
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case GPU_REG_INDEX(command_processor_config.trigger):
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{
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const auto& config = g_regs.command_processor_config;
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if (config.trigger & 1)
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{
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u32* buffer = (u32*)Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetPhysicalAddress()));
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Pica::CommandProcessor::ProcessCommandList(buffer, config.size);
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}
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break;
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}
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default:
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break;
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}
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}
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// Explicitly instantiate template functions because we aren't defining this in the header:
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template void Read<u64>(u64 &var, const u32 addr);
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template void Read<u32>(u32 &var, const u32 addr);
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template void Read<u16>(u16 &var, const u32 addr);
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template void Read<u8>(u8 &var, const u32 addr);
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template void Write<u64>(u32 addr, const u64 data);
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template void Write<u32>(u32 addr, const u32 data);
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template void Write<u16>(u32 addr, const u16 data);
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template void Write<u8>(u32 addr, const u8 data);
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/// Update hardware
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void Update() {
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auto& framebuffer_top = g_regs.framebuffer_config[0];
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// Synchronize GPU on a thread reschedule: Because we cannot accurately predict a vertical
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// blank, we need to simulate it. Based on testing, it seems that retail applications work more
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// accurately when this is signalled between thread switches.
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if (HLE::g_reschedule) {
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u64 current_ticks = Core::g_app_core->GetTicks();
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u32 num_lines = static_cast<u32>((current_ticks - last_update_tick) / line_ticks);
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// Synchronize line...
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if (num_lines > 0) {
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PDC0);
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cur_line += num_lines;
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last_update_tick += (num_lines * line_ticks);
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}
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// Synchronize frame...
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if (cur_line >= framebuffer_top.height) {
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cur_line = 0;
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frame_count++;
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last_skip_frame = g_skip_frame;
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g_skip_frame = (frame_count & Settings::values.frame_skip) != 0;
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// Swap buffers based on the frameskip mode, which is a little bit tricky. When
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// a frame is being skipped, nothing is being rendered to the internal framebuffer(s).
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// So, we should only swap frames if the last frame was rendered. The rules are:
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// - If frameskip == 0 (disabled), always swap buffers
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// - If frameskip == 1, swap buffers every other frame (starting from the first frame)
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// - If frameskip > 1, swap buffers every frameskip^n frames (starting from the second frame)
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if ((((Settings::values.frame_skip != 1) ^ last_skip_frame) && last_skip_frame != g_skip_frame) ||
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Settings::values.frame_skip == 0) {
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VideoCore::g_renderer->SwapBuffers();
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}
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PDC1);
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}
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}
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}
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/// Initialize hardware
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void Init() {
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auto& framebuffer_top = g_regs.framebuffer_config[0];
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auto& framebuffer_sub = g_regs.framebuffer_config[1];
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// Setup default framebuffer addresses (located in VRAM)
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// .. or at least these are the ones used by system applets.
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// There's probably a smarter way to come up with addresses
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// like this which does not require hardcoding.
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framebuffer_top.address_left1 = 0x181E6000;
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framebuffer_top.address_left2 = 0x1822C800;
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framebuffer_top.address_right1 = 0x18273000;
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framebuffer_top.address_right2 = 0x182B9800;
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framebuffer_sub.address_left1 = 0x1848F000;
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//framebuffer_sub.address_left2 = unknown;
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framebuffer_sub.address_right1 = 0x184C7800;
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//framebuffer_sub.address_right2 = unknown;
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framebuffer_top.width = 240;
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framebuffer_top.height = 400;
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framebuffer_top.stride = 3 * 240;
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framebuffer_top.color_format = Regs::PixelFormat::RGB8;
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framebuffer_top.active_fb = 0;
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framebuffer_sub.width = 240;
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framebuffer_sub.height = 320;
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framebuffer_sub.stride = 3 * 240;
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framebuffer_sub.color_format = Regs::PixelFormat::RGB8;
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framebuffer_sub.active_fb = 0;
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frame_ticks = 268123480 / Settings::values.gpu_refresh_rate;
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line_ticks = (GPU::frame_ticks / framebuffer_top.height);
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cur_line = 0;
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last_update_tick = Core::g_app_core->GetTicks();
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last_skip_frame = false;
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g_skip_frame = false;
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LOG_DEBUG(HW_GPU, "initialized OK");
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}
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/// Shutdown hardware
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void Shutdown() {
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LOG_DEBUG(HW_GPU, "shutdown OK");
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}
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} // namespace
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