99ceb03a1c
This formats all copyright comments according to SPDX formatting guidelines. Additionally, this resolves the remaining GPLv2 only licensed files by relicensing them to GPLv2.0-or-later.
302 lines
10 KiB
C++
302 lines
10 KiB
C++
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/backend/glasm/emit_glasm_instructions.h"
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#include "shader_recompiler/backend/glasm/glasm_emit_context.h"
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#include "shader_recompiler/frontend/ir/value.h"
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namespace Shader::Backend::GLASM {
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namespace {
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void BitwiseLogicalOp(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b,
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std::string_view lop) {
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const auto zero = inst.GetAssociatedPseudoOperation(IR::Opcode::GetZeroFromOp);
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const auto sign = inst.GetAssociatedPseudoOperation(IR::Opcode::GetSignFromOp);
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if (zero) {
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zero->Invalidate();
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}
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if (sign) {
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sign->Invalidate();
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}
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if (zero || sign) {
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ctx.reg_alloc.InvalidateConditionCodes();
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}
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const auto ret{ctx.reg_alloc.Define(inst)};
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ctx.Add("{}.S {}.x,{},{};", lop, ret, a, b);
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if (zero) {
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ctx.Add("SEQ.S {},{},0;", *zero, ret);
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}
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if (sign) {
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ctx.Add("SLT.S {},{},0;", *sign, ret);
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}
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}
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} // Anonymous namespace
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void EmitIAdd32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
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const std::array flags{
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inst.GetAssociatedPseudoOperation(IR::Opcode::GetZeroFromOp),
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inst.GetAssociatedPseudoOperation(IR::Opcode::GetSignFromOp),
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inst.GetAssociatedPseudoOperation(IR::Opcode::GetCarryFromOp),
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inst.GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp),
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};
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for (IR::Inst* const flag_inst : flags) {
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if (flag_inst) {
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flag_inst->Invalidate();
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}
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}
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const bool cc{inst.HasAssociatedPseudoOperation()};
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const std::string_view cc_mod{cc ? ".CC" : ""};
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if (cc) {
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ctx.reg_alloc.InvalidateConditionCodes();
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}
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const auto ret{ctx.reg_alloc.Define(inst)};
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ctx.Add("ADD.S{} {}.x,{},{};", cc_mod, ret, a, b);
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if (!cc) {
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return;
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}
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static constexpr std::array<std::string_view, 4> masks{"", "SF", "CF", "OF"};
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for (size_t flag_index = 0; flag_index < flags.size(); ++flag_index) {
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if (!flags[flag_index]) {
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continue;
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}
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const auto flag_ret{ctx.reg_alloc.Define(*flags[flag_index])};
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if (flag_index == 0) {
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ctx.Add("SEQ.S {}.x,{}.x,0;", flag_ret, ret);
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} else {
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// We could use conditional execution here, but it's broken on Nvidia's compiler
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ctx.Add("IF {}.x;"
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"MOV.S {}.x,-1;"
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"ELSE;"
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"MOV.S {}.x,0;"
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"ENDIF;",
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masks[flag_index], flag_ret, flag_ret);
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}
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}
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}
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void EmitIAdd64(EmitContext& ctx, IR::Inst& inst, Register a, Register b) {
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ctx.LongAdd("ADD.S64 {}.x,{}.x,{}.x;", inst, a, b);
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}
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void EmitISub32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
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ctx.Add("SUB.S {}.x,{},{};", inst, a, b);
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}
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void EmitISub64(EmitContext& ctx, IR::Inst& inst, Register a, Register b) {
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ctx.LongAdd("SUB.S64 {}.x,{}.x,{}.x;", inst, a, b);
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}
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void EmitIMul32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
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ctx.Add("MUL.S {}.x,{},{};", inst, a, b);
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}
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void EmitSDiv32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
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ctx.Add("DIV.S {}.x,{},{};", inst, a, b);
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}
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void EmitUDiv32(EmitContext& ctx, IR::Inst& inst, ScalarU32 a, ScalarU32 b) {
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ctx.Add("DIV.U {}.x,{},{};", inst, a, b);
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}
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void EmitINeg32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) {
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if (value.type != Type::Register && static_cast<s32>(value.imm_u32) < 0) {
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ctx.Add("MOV.S {},{};", inst, -static_cast<s32>(value.imm_u32));
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} else {
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ctx.Add("MOV.S {},-{};", inst, value);
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}
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}
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void EmitINeg64(EmitContext& ctx, IR::Inst& inst, Register value) {
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ctx.LongAdd("MOV.S64 {},-{};", inst, value);
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}
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void EmitIAbs32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) {
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ctx.Add("ABS.S {},{};", inst, value);
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}
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void EmitShiftLeftLogical32(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 shift) {
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ctx.Add("SHL.U {}.x,{},{};", inst, base, shift);
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}
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void EmitShiftLeftLogical64(EmitContext& ctx, IR::Inst& inst, ScalarRegister base,
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ScalarU32 shift) {
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ctx.LongAdd("SHL.U64 {}.x,{},{};", inst, base, shift);
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}
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void EmitShiftRightLogical32(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 shift) {
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ctx.Add("SHR.U {}.x,{},{};", inst, base, shift);
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}
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void EmitShiftRightLogical64(EmitContext& ctx, IR::Inst& inst, ScalarRegister base,
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ScalarU32 shift) {
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ctx.LongAdd("SHR.U64 {}.x,{},{};", inst, base, shift);
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}
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void EmitShiftRightArithmetic32(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 shift) {
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ctx.Add("SHR.S {}.x,{},{};", inst, base, shift);
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}
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void EmitShiftRightArithmetic64(EmitContext& ctx, IR::Inst& inst, ScalarRegister base,
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ScalarS32 shift) {
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ctx.LongAdd("SHR.S64 {}.x,{},{};", inst, base, shift);
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}
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void EmitBitwiseAnd32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
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BitwiseLogicalOp(ctx, inst, a, b, "AND");
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}
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void EmitBitwiseOr32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
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BitwiseLogicalOp(ctx, inst, a, b, "OR");
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}
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void EmitBitwiseXor32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
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BitwiseLogicalOp(ctx, inst, a, b, "XOR");
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}
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void EmitBitFieldInsert(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 insert,
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ScalarS32 offset, ScalarS32 count) {
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const Register ret{ctx.reg_alloc.Define(inst)};
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if (count.type != Type::Register && offset.type != Type::Register) {
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ctx.Add("BFI.S {},{{{},{},0,0}},{},{};", ret, count, offset, insert, base);
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} else {
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ctx.Add("MOV.S RC.x,{};"
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"MOV.S RC.y,{};"
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"BFI.S {},RC,{},{};",
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count, offset, ret, insert, base);
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}
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}
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void EmitBitFieldSExtract(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 offset,
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ScalarS32 count) {
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const Register ret{ctx.reg_alloc.Define(inst)};
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if (count.type != Type::Register && offset.type != Type::Register) {
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ctx.Add("BFE.S {},{{{},{},0,0}},{};", ret, count, offset, base);
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} else {
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ctx.Add("MOV.S RC.x,{};"
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"MOV.S RC.y,{};"
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"BFE.S {},RC,{};",
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count, offset, ret, base);
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}
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}
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void EmitBitFieldUExtract(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 offset,
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ScalarU32 count) {
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const auto zero = inst.GetAssociatedPseudoOperation(IR::Opcode::GetZeroFromOp);
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const auto sign = inst.GetAssociatedPseudoOperation(IR::Opcode::GetSignFromOp);
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if (zero) {
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zero->Invalidate();
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}
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if (sign) {
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sign->Invalidate();
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}
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if (zero || sign) {
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ctx.reg_alloc.InvalidateConditionCodes();
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}
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const Register ret{ctx.reg_alloc.Define(inst)};
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if (count.type != Type::Register && offset.type != Type::Register) {
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ctx.Add("BFE.U {},{{{},{},0,0}},{};", ret, count, offset, base);
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} else {
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ctx.Add("MOV.U RC.x,{};"
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"MOV.U RC.y,{};"
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"BFE.U {},RC,{};",
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count, offset, ret, base);
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}
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if (zero) {
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ctx.Add("SEQ.S {},{},0;", *zero, ret);
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}
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if (sign) {
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ctx.Add("SLT.S {},{},0;", *sign, ret);
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}
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}
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void EmitBitReverse32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) {
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ctx.Add("BFR {},{};", inst, value);
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}
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void EmitBitCount32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) {
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ctx.Add("BTC {},{};", inst, value);
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}
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void EmitBitwiseNot32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) {
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ctx.Add("NOT.S {},{};", inst, value);
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}
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void EmitFindSMsb32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) {
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ctx.Add("BTFM.S {},{};", inst, value);
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}
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void EmitFindUMsb32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value) {
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ctx.Add("BTFM.U {},{};", inst, value);
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}
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void EmitSMin32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
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ctx.Add("MIN.S {},{},{};", inst, a, b);
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}
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void EmitUMin32(EmitContext& ctx, IR::Inst& inst, ScalarU32 a, ScalarU32 b) {
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ctx.Add("MIN.U {},{},{};", inst, a, b);
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}
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void EmitSMax32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
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ctx.Add("MAX.S {},{},{};", inst, a, b);
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}
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void EmitUMax32(EmitContext& ctx, IR::Inst& inst, ScalarU32 a, ScalarU32 b) {
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ctx.Add("MAX.U {},{},{};", inst, a, b);
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}
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void EmitSClamp32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value, ScalarS32 min, ScalarS32 max) {
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const Register ret{ctx.reg_alloc.Define(inst)};
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ctx.Add("MIN.S RC.x,{},{};"
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"MAX.S {}.x,RC.x,{};",
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max, value, ret, min);
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}
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void EmitUClamp32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 min, ScalarU32 max) {
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const Register ret{ctx.reg_alloc.Define(inst)};
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ctx.Add("MIN.U RC.x,{},{};"
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"MAX.U {}.x,RC.x,{};",
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max, value, ret, min);
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}
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void EmitSLessThan(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs) {
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ctx.Add("SLT.S {}.x,{},{};", inst, lhs, rhs);
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}
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void EmitULessThan(EmitContext& ctx, IR::Inst& inst, ScalarU32 lhs, ScalarU32 rhs) {
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ctx.Add("SLT.U {}.x,{},{};", inst, lhs, rhs);
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}
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void EmitIEqual(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs) {
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ctx.Add("SEQ.S {}.x,{},{};", inst, lhs, rhs);
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}
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void EmitSLessThanEqual(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs) {
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ctx.Add("SLE.S {}.x,{},{};", inst, lhs, rhs);
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}
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void EmitULessThanEqual(EmitContext& ctx, IR::Inst& inst, ScalarU32 lhs, ScalarU32 rhs) {
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ctx.Add("SLE.U {}.x,{},{};", inst, lhs, rhs);
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}
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void EmitSGreaterThan(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs) {
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ctx.Add("SGT.S {}.x,{},{};", inst, lhs, rhs);
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}
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void EmitUGreaterThan(EmitContext& ctx, IR::Inst& inst, ScalarU32 lhs, ScalarU32 rhs) {
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ctx.Add("SGT.U {}.x,{},{};", inst, lhs, rhs);
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}
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void EmitINotEqual(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs) {
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ctx.Add("SNE.U {}.x,{},{};", inst, lhs, rhs);
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}
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void EmitSGreaterThanEqual(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs) {
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ctx.Add("SGE.S {}.x,{},{};", inst, lhs, rhs);
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}
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void EmitUGreaterThanEqual(EmitContext& ctx, IR::Inst& inst, ScalarU32 lhs, ScalarU32 rhs) {
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ctx.Add("SGE.U {}.x,{},{};", inst, lhs, rhs);
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}
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} // namespace Shader::Backend::GLASM
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