core: Implement separate A32/A64 ARM interfaces.
This commit is contained in:
bunnei
parent
6fc485a607
commit
c083ea7d78
21 changed files with 454 additions and 122 deletions
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@ -595,8 +595,10 @@ endif()
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if (ARCHITECTURE_x86_64)
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target_sources(core PRIVATE
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arm/dynarmic/arm_dynarmic.cpp
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arm/dynarmic/arm_dynarmic.h
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arm/dynarmic/arm_dynarmic_32.cpp
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arm/dynarmic/arm_dynarmic_32.h
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arm/dynarmic/arm_dynarmic_64.cpp
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arm/dynarmic/arm_dynarmic_64.h
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arm/dynarmic/arm_dynarmic_cp15.cpp
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arm/dynarmic/arm_dynarmic_cp15.h
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)
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@ -25,7 +25,20 @@ public:
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explicit ARM_Interface(System& system_) : system{system_} {}
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virtual ~ARM_Interface() = default;
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struct ThreadContext {
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struct ThreadContext32 {
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std::array<u32, 16> cpu_registers;
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u32 cpsr;
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std::array<u8, 4> padding;
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std::array<u64, 32> fprs;
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u32 fpscr;
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u32 fpexc;
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u32 tpidr;
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};
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// Internally within the kernel, it expects the AArch32 version of the
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// thread context to be 344 bytes in size.
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static_assert(sizeof(ThreadContext32) == 0x158);
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struct ThreadContext64 {
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std::array<u64, 31> cpu_registers;
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u64 sp;
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u64 pc;
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@ -38,7 +51,7 @@ public:
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};
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// Internally within the kernel, it expects the AArch64 version of the
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// thread context to be 800 bytes in size.
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static_assert(sizeof(ThreadContext) == 0x320);
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static_assert(sizeof(ThreadContext64) == 0x320);
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/// Runs the CPU until an event happens
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virtual void Run() = 0;
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@ -130,17 +143,10 @@ public:
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*/
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virtual void SetTPIDR_EL0(u64 value) = 0;
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/**
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* Saves the current CPU context
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* @param ctx Thread context to save
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*/
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virtual void SaveContext(ThreadContext& ctx) = 0;
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/**
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* Loads a CPU context
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* @param ctx Thread context to load
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*/
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virtual void LoadContext(const ThreadContext& ctx) = 0;
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virtual void SaveContext(ThreadContext32& ctx) = 0;
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virtual void SaveContext(ThreadContext64& ctx) = 0;
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virtual void LoadContext(const ThreadContext32& ctx) = 0;
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virtual void LoadContext(const ThreadContext64& ctx) = 0;
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/// Clears the exclusive monitor's state.
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virtual void ClearExclusiveState() = 0;
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208
src/core/arm/dynarmic/arm_dynarmic_32.cpp
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208
src/core/arm/dynarmic/arm_dynarmic_32.cpp
Normal file
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@ -0,0 +1,208 @@
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// Copyright 2020 yuzu emulator team
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cinttypes>
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#include <memory>
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#include <dynarmic/A32/a32.h>
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#include <dynarmic/A32/config.h>
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#include <dynarmic/A32/context.h>
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#include "common/microprofile.h"
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#include "core/arm/dynarmic/arm_dynarmic_32.h"
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#include "core/arm/dynarmic/arm_dynarmic_64.h"
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#include "core/arm/dynarmic/arm_dynarmic_cp15.h"
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#include "core/core.h"
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#include "core/core_manager.h"
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#include "core/core_timing.h"
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#include "core/hle/kernel/svc.h"
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#include "core/memory.h"
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namespace Core {
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class DynarmicCallbacks32 : public Dynarmic::A32::UserCallbacks {
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public:
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explicit DynarmicCallbacks32(ARM_Dynarmic_32& parent) : parent(parent) {}
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u8 MemoryRead8(u32 vaddr) override {
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return parent.system.Memory().Read8(vaddr);
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}
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u16 MemoryRead16(u32 vaddr) override {
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return parent.system.Memory().Read16(vaddr);
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}
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u32 MemoryRead32(u32 vaddr) override {
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return parent.system.Memory().Read32(vaddr);
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}
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u64 MemoryRead64(u32 vaddr) override {
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return parent.system.Memory().Read64(vaddr);
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}
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void MemoryWrite8(u32 vaddr, u8 value) override {
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parent.system.Memory().Write8(vaddr, value);
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}
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void MemoryWrite16(u32 vaddr, u16 value) override {
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parent.system.Memory().Write16(vaddr, value);
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}
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void MemoryWrite32(u32 vaddr, u32 value) override {
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parent.system.Memory().Write32(vaddr, value);
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}
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void MemoryWrite64(u32 vaddr, u64 value) override {
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parent.system.Memory().Write64(vaddr, value);
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}
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void InterpreterFallback(u32 pc, std::size_t num_instructions) override {
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UNIMPLEMENTED();
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}
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void ExceptionRaised(u32 pc, Dynarmic::A32::Exception exception) override {
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switch (exception) {
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case Dynarmic::A32::Exception::UndefinedInstruction:
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case Dynarmic::A32::Exception::UnpredictableInstruction:
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break;
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case Dynarmic::A32::Exception::Breakpoint:
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break;
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}
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LOG_CRITICAL(HW_GPU, "ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X})",
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static_cast<std::size_t>(exception), pc, MemoryReadCode(pc));
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UNIMPLEMENTED();
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}
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void CallSVC(u32 swi) override {
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Kernel::CallSVC(parent.system, swi);
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}
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void AddTicks(u64 ticks) override {
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// Divide the number of ticks by the amount of CPU cores. TODO(Subv): This yields only a
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// rough approximation of the amount of executed ticks in the system, it may be thrown off
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// if not all cores are doing a similar amount of work. Instead of doing this, we should
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// device a way so that timing is consistent across all cores without increasing the ticks 4
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// times.
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u64 amortized_ticks = (ticks - num_interpreted_instructions) / Core::NUM_CPU_CORES;
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// Always execute at least one tick.
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amortized_ticks = std::max<u64>(amortized_ticks, 1);
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parent.system.CoreTiming().AddTicks(amortized_ticks);
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num_interpreted_instructions = 0;
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}
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u64 GetTicksRemaining() override {
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return std::max(parent.system.CoreTiming().GetDowncount(), {});
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}
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ARM_Dynarmic_32& parent;
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std::size_t num_interpreted_instructions{};
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u64 tpidrro_el0{};
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u64 tpidr_el0{};
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};
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std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable& page_table,
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std::size_t address_space_bits) const {
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Dynarmic::A32::UserConfig config;
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config.callbacks = cb.get();
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// TODO(bunnei): Implement page table for 32-bit
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// config.page_table = &page_table.pointers;
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config.coprocessors[15] = std::make_shared<DynarmicCP15>((u32*)&CP15_regs[0]);
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config.define_unpredictable_behaviour = true;
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return std::make_unique<Dynarmic::A32::Jit>(config);
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}
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MICROPROFILE_DEFINE(ARM_Jit_Dynarmic_32, "ARM JIT", "Dynarmic", MP_RGB(255, 64, 64));
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void ARM_Dynarmic_32::Run() {
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MICROPROFILE_SCOPE(ARM_Jit_Dynarmic_32);
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jit->Run();
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}
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void ARM_Dynarmic_32::Step() {
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cb->InterpreterFallback(jit->Regs()[15], 1);
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}
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ARM_Dynarmic_32::ARM_Dynarmic_32(System& system, ExclusiveMonitor& exclusive_monitor,
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std::size_t core_index)
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: ARM_Interface{system},
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cb(std::make_unique<DynarmicCallbacks32>(*this)), core_index{core_index},
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exclusive_monitor{dynamic_cast<DynarmicExclusiveMonitor&>(exclusive_monitor)} {}
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ARM_Dynarmic_32::~ARM_Dynarmic_32() = default;
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void ARM_Dynarmic_32::SetPC(u64 pc) {
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jit->Regs()[15] = static_cast<u32>(pc);
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}
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u64 ARM_Dynarmic_32::GetPC() const {
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return jit->Regs()[15];
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}
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u64 ARM_Dynarmic_32::GetReg(int index) const {
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return jit->Regs()[index];
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}
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void ARM_Dynarmic_32::SetReg(int index, u64 value) {
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jit->Regs()[index] = static_cast<u32>(value);
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}
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u128 ARM_Dynarmic_32::GetVectorReg(int index) const {
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return {};
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}
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void ARM_Dynarmic_32::SetVectorReg(int index, u128 value) {}
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u32 ARM_Dynarmic_32::GetPSTATE() const {
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return jit->Cpsr();
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}
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void ARM_Dynarmic_32::SetPSTATE(u32 cpsr) {
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jit->SetCpsr(cpsr);
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}
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u64 ARM_Dynarmic_32::GetTlsAddress() const {
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return CP15_regs[static_cast<std::size_t>(CP15Register::CP15_THREAD_URO)];
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}
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void ARM_Dynarmic_32::SetTlsAddress(VAddr address) {
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CP15_regs[static_cast<std::size_t>(CP15Register::CP15_THREAD_URO)] = static_cast<u32>(address);
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}
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u64 ARM_Dynarmic_32::GetTPIDR_EL0() const {
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return cb->tpidr_el0;
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}
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void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) {
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cb->tpidr_el0 = value;
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}
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void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
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Dynarmic::A32::Context context;
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jit->SaveContext(context);
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ctx.cpu_registers = context.Regs();
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ctx.cpsr = context.Cpsr();
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}
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void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
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Dynarmic::A32::Context context;
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context.Regs() = ctx.cpu_registers;
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context.SetCpsr(ctx.cpsr);
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jit->LoadContext(context);
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}
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void ARM_Dynarmic_32::PrepareReschedule() {
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jit->HaltExecution();
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}
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void ARM_Dynarmic_32::ClearInstructionCache() {
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jit->ClearCache();
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}
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void ARM_Dynarmic_32::ClearExclusiveState() {}
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void ARM_Dynarmic_32::PageTableChanged(Common::PageTable& page_table,
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std::size_t new_address_space_size_in_bits) {
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auto key = std::make_pair(&page_table, new_address_space_size_in_bits);
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auto iter = jit_cache.find(key);
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if (iter != jit_cache.end()) {
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jit = iter->second;
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return;
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}
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jit = MakeJit(page_table, new_address_space_size_in_bits);
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jit_cache.emplace(key, jit);
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}
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} // namespace Core
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77
src/core/arm/dynarmic/arm_dynarmic_32.h
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77
src/core/arm/dynarmic/arm_dynarmic_32.h
Normal file
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@ -0,0 +1,77 @@
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// Copyright 2020 yuzu emulator team
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <memory>
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#include <unordered_map>
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#include <dynarmic/A32/a32.h>
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#include <dynarmic/A64/a64.h>
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#include <dynarmic/A64/exclusive_monitor.h>
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#include "common/common_types.h"
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#include "common/hash.h"
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#include "core/arm/arm_interface.h"
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#include "core/arm/exclusive_monitor.h"
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namespace Memory {
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class Memory;
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}
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namespace Core {
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class DynarmicCallbacks32;
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class DynarmicExclusiveMonitor;
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class System;
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class ARM_Dynarmic_32 final : public ARM_Interface {
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public:
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ARM_Dynarmic_32(System& system, ExclusiveMonitor& exclusive_monitor, std::size_t core_index);
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~ARM_Dynarmic_32() override;
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void SetPC(u64 pc) override;
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u64 GetPC() const override;
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u64 GetReg(int index) const override;
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void SetReg(int index, u64 value) override;
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u128 GetVectorReg(int index) const override;
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void SetVectorReg(int index, u128 value) override;
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u32 GetPSTATE() const override;
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void SetPSTATE(u32 pstate) override;
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void Run() override;
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void Step() override;
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VAddr GetTlsAddress() const override;
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void SetTlsAddress(VAddr address) override;
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void SetTPIDR_EL0(u64 value) override;
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u64 GetTPIDR_EL0() const override;
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void SaveContext(ThreadContext32& ctx) override;
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void SaveContext(ThreadContext64& ctx) override {}
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void LoadContext(const ThreadContext32& ctx) override;
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void LoadContext(const ThreadContext64& ctx) override {}
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void PrepareReschedule() override;
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void ClearExclusiveState() override;
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void ClearInstructionCache() override;
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void PageTableChanged(Common::PageTable& new_page_table,
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std::size_t new_address_space_size_in_bits) override;
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private:
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std::shared_ptr<Dynarmic::A32::Jit> MakeJit(Common::PageTable& page_table,
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std::size_t address_space_bits) const;
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using JitCacheKey = std::pair<Common::PageTable*, std::size_t>;
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using JitCacheType =
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std::unordered_map<JitCacheKey, std::shared_ptr<Dynarmic::A32::Jit>, Common::PairHash>;
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friend class DynarmicCallbacks32;
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std::unique_ptr<DynarmicCallbacks32> cb;
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JitCacheType jit_cache;
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std::shared_ptr<Dynarmic::A32::Jit> jit;
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std::size_t core_index;
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DynarmicExclusiveMonitor& exclusive_monitor;
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std::array<u32, 84> CP15_regs{};
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};
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} // namespace Core
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@ -8,7 +8,7 @@
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#include <dynarmic/A64/config.h>
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#include "common/logging/log.h"
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#include "common/microprofile.h"
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#include "core/arm/dynarmic/arm_dynarmic.h"
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#include "core/arm/dynarmic/arm_dynarmic_64.h"
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#include "core/core.h"
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#include "core/core_manager.h"
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#include "core/core_timing.h"
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@ -25,9 +25,9 @@ namespace Core {
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using Vector = Dynarmic::A64::Vector;
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class ARM_Dynarmic_Callbacks : public Dynarmic::A64::UserCallbacks {
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class DynarmicCallbacks64 : public Dynarmic::A64::UserCallbacks {
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public:
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explicit ARM_Dynarmic_Callbacks(ARM_Dynarmic& parent) : parent(parent) {}
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explicit DynarmicCallbacks64(ARM_Dynarmic_64& parent) : parent(parent) {}
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u8 MemoryRead8(u64 vaddr) override {
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return parent.system.Memory().Read8(vaddr);
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@ -68,7 +68,7 @@ public:
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LOG_INFO(Core_ARM, "Unicorn fallback @ 0x{:X} for {} instructions (instr = {:08X})", pc,
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num_instructions, MemoryReadCode(pc));
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ARM_Interface::ThreadContext ctx;
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ARM_Interface::ThreadContext64 ctx;
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parent.SaveContext(ctx);
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parent.inner_unicorn.LoadContext(ctx);
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parent.inner_unicorn.ExecuteInstructions(num_instructions);
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@ -90,7 +90,7 @@ public:
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parent.jit->HaltExecution();
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parent.SetPC(pc);
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Kernel::Thread* const thread = parent.system.CurrentScheduler().GetCurrentThread();
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parent.SaveContext(thread->GetContext());
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parent.SaveContext(thread->GetContext64());
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GDBStub::Break();
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GDBStub::SendTrap(thread, 5);
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return;
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@ -126,13 +126,13 @@ public:
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return Timing::CpuCyclesToClockCycles(parent.system.CoreTiming().GetTicks());
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}
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ARM_Dynarmic& parent;
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ARM_Dynarmic_64& parent;
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std::size_t num_interpreted_instructions = 0;
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u64 tpidrro_el0 = 0;
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u64 tpidr_el0 = 0;
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};
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std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic::MakeJit(Common::PageTable& page_table,
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std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable& page_table,
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std::size_t address_space_bits) const {
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Dynarmic::A64::UserConfig config;
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@ -162,76 +162,76 @@ std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic::MakeJit(Common::PageTable& pag
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return std::make_shared<Dynarmic::A64::Jit>(config);
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}
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MICROPROFILE_DEFINE(ARM_Jit_Dynarmic, "ARM JIT", "Dynarmic", MP_RGB(255, 64, 64));
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MICROPROFILE_DEFINE(ARM_Jit_Dynarmic_64, "ARM JIT", "Dynarmic", MP_RGB(255, 64, 64));
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void ARM_Dynarmic::Run() {
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MICROPROFILE_SCOPE(ARM_Jit_Dynarmic);
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void ARM_Dynarmic_64::Run() {
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MICROPROFILE_SCOPE(ARM_Jit_Dynarmic_64);
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jit->Run();
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}
|
||||
|
||||
void ARM_Dynarmic::Step() {
|
||||
void ARM_Dynarmic_64::Step() {
|
||||
cb->InterpreterFallback(jit->GetPC(), 1);
|
||||
}
|
||||
|
||||
ARM_Dynarmic::ARM_Dynarmic(System& system, ExclusiveMonitor& exclusive_monitor,
|
||||
ARM_Dynarmic_64::ARM_Dynarmic_64(System& system, ExclusiveMonitor& exclusive_monitor,
|
||||
std::size_t core_index)
|
||||
: ARM_Interface{system},
|
||||
cb(std::make_unique<ARM_Dynarmic_Callbacks>(*this)), inner_unicorn{system},
|
||||
cb(std::make_unique<DynarmicCallbacks64>(*this)), inner_unicorn{system},
|
||||
core_index{core_index}, exclusive_monitor{
|
||||
dynamic_cast<DynarmicExclusiveMonitor&>(exclusive_monitor)} {}
|
||||
|
||||
ARM_Dynarmic::~ARM_Dynarmic() = default;
|
||||
ARM_Dynarmic_64::~ARM_Dynarmic_64() = default;
|
||||
|
||||
void ARM_Dynarmic::SetPC(u64 pc) {
|
||||
void ARM_Dynarmic_64::SetPC(u64 pc) {
|
||||
jit->SetPC(pc);
|
||||
}
|
||||
|
||||
u64 ARM_Dynarmic::GetPC() const {
|
||||
u64 ARM_Dynarmic_64::GetPC() const {
|
||||
return jit->GetPC();
|
||||
}
|
||||
|
||||
u64 ARM_Dynarmic::GetReg(int index) const {
|
||||
u64 ARM_Dynarmic_64::GetReg(int index) const {
|
||||
return jit->GetRegister(index);
|
||||
}
|
||||
|
||||
void ARM_Dynarmic::SetReg(int index, u64 value) {
|
||||
void ARM_Dynarmic_64::SetReg(int index, u64 value) {
|
||||
jit->SetRegister(index, value);
|
||||
}
|
||||
|
||||
u128 ARM_Dynarmic::GetVectorReg(int index) const {
|
||||
u128 ARM_Dynarmic_64::GetVectorReg(int index) const {
|
||||
return jit->GetVector(index);
|
||||
}
|
||||
|
||||
void ARM_Dynarmic::SetVectorReg(int index, u128 value) {
|
||||
void ARM_Dynarmic_64::SetVectorReg(int index, u128 value) {
|
||||
jit->SetVector(index, value);
|
||||
}
|
||||
|
||||
u32 ARM_Dynarmic::GetPSTATE() const {
|
||||
u32 ARM_Dynarmic_64::GetPSTATE() const {
|
||||
return jit->GetPstate();
|
||||
}
|
||||
|
||||
void ARM_Dynarmic::SetPSTATE(u32 pstate) {
|
||||
void ARM_Dynarmic_64::SetPSTATE(u32 pstate) {
|
||||
jit->SetPstate(pstate);
|
||||
}
|
||||
|
||||
u64 ARM_Dynarmic::GetTlsAddress() const {
|
||||
u64 ARM_Dynarmic_64::GetTlsAddress() const {
|
||||
return cb->tpidrro_el0;
|
||||
}
|
||||
|
||||
void ARM_Dynarmic::SetTlsAddress(VAddr address) {
|
||||
void ARM_Dynarmic_64::SetTlsAddress(VAddr address) {
|
||||
cb->tpidrro_el0 = address;
|
||||
}
|
||||
|
||||
u64 ARM_Dynarmic::GetTPIDR_EL0() const {
|
||||
u64 ARM_Dynarmic_64::GetTPIDR_EL0() const {
|
||||
return cb->tpidr_el0;
|
||||
}
|
||||
|
||||
void ARM_Dynarmic::SetTPIDR_EL0(u64 value) {
|
||||
void ARM_Dynarmic_64::SetTPIDR_EL0(u64 value) {
|
||||
cb->tpidr_el0 = value;
|
||||
}
|
||||
|
||||
void ARM_Dynarmic::SaveContext(ThreadContext& ctx) {
|
||||
void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) {
|
||||
ctx.cpu_registers = jit->GetRegisters();
|
||||
ctx.sp = jit->GetSP();
|
||||
ctx.pc = jit->GetPC();
|
||||
|
|
@ -242,7 +242,7 @@ void ARM_Dynarmic::SaveContext(ThreadContext& ctx) {
|
|||
ctx.tpidr = cb->tpidr_el0;
|
||||
}
|
||||
|
||||
void ARM_Dynarmic::LoadContext(const ThreadContext& ctx) {
|
||||
void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) {
|
||||
jit->SetRegisters(ctx.cpu_registers);
|
||||
jit->SetSP(ctx.sp);
|
||||
jit->SetPC(ctx.pc);
|
||||
|
|
@ -253,19 +253,19 @@ void ARM_Dynarmic::LoadContext(const ThreadContext& ctx) {
|
|||
SetTPIDR_EL0(ctx.tpidr);
|
||||
}
|
||||
|
||||
void ARM_Dynarmic::PrepareReschedule() {
|
||||
void ARM_Dynarmic_64::PrepareReschedule() {
|
||||
jit->HaltExecution();
|
||||
}
|
||||
|
||||
void ARM_Dynarmic::ClearInstructionCache() {
|
||||
void ARM_Dynarmic_64::ClearInstructionCache() {
|
||||
jit->ClearCache();
|
||||
}
|
||||
|
||||
void ARM_Dynarmic::ClearExclusiveState() {
|
||||
void ARM_Dynarmic_64::ClearExclusiveState() {
|
||||
jit->ClearExclusiveState();
|
||||
}
|
||||
|
||||
void ARM_Dynarmic::PageTableChanged(Common::PageTable& page_table,
|
||||
void ARM_Dynarmic_64::PageTableChanged(Common::PageTable& page_table,
|
||||
std::size_t new_address_space_size_in_bits) {
|
||||
auto key = std::make_pair(&page_table, new_address_space_size_in_bits);
|
||||
auto iter = jit_cache.find(key);
|
||||
|
|
@ -277,8 +277,8 @@ void ARM_Dynarmic::PageTableChanged(Common::PageTable& page_table,
|
|||
jit_cache.emplace(key, jit);
|
||||
}
|
||||
|
||||
DynarmicExclusiveMonitor::DynarmicExclusiveMonitor(Memory::Memory& memory_, std::size_t core_count)
|
||||
: monitor(core_count), memory{memory_} {}
|
||||
DynarmicExclusiveMonitor::DynarmicExclusiveMonitor(Memory::Memory& memory, std::size_t core_count)
|
||||
: monitor(core_count), memory{memory} {}
|
||||
|
||||
DynarmicExclusiveMonitor::~DynarmicExclusiveMonitor() = default;
|
||||
|
||||
|
|
@ -21,18 +21,14 @@ class Memory;
|
|||
|
||||
namespace Core {
|
||||
|
||||
class ARM_Dynarmic_Callbacks;
|
||||
class DynarmicCallbacks64;
|
||||
class DynarmicExclusiveMonitor;
|
||||
class System;
|
||||
|
||||
using JitCacheKey = std::pair<Common::PageTable*, std::size_t>;
|
||||
using JitCacheType =
|
||||
std::unordered_map<JitCacheKey, std::shared_ptr<Dynarmic::A64::Jit>, Common::PairHash>;
|
||||
|
||||
class ARM_Dynarmic final : public ARM_Interface {
|
||||
class ARM_Dynarmic_64 final : public ARM_Interface {
|
||||
public:
|
||||
ARM_Dynarmic(System& system, ExclusiveMonitor& exclusive_monitor, std::size_t core_index);
|
||||
~ARM_Dynarmic() override;
|
||||
ARM_Dynarmic_64(System& system, ExclusiveMonitor& exclusive_monitor, std::size_t core_index);
|
||||
~ARM_Dynarmic_64() override;
|
||||
|
||||
void SetPC(u64 pc) override;
|
||||
u64 GetPC() const override;
|
||||
|
|
@ -49,8 +45,10 @@ public:
|
|||
void SetTPIDR_EL0(u64 value) override;
|
||||
u64 GetTPIDR_EL0() const override;
|
||||
|
||||
void SaveContext(ThreadContext& ctx) override;
|
||||
void LoadContext(const ThreadContext& ctx) override;
|
||||
void SaveContext(ThreadContext32& ctx) override {}
|
||||
void SaveContext(ThreadContext64& ctx) override;
|
||||
void LoadContext(const ThreadContext32& ctx) override {}
|
||||
void LoadContext(const ThreadContext64& ctx) override;
|
||||
|
||||
void PrepareReschedule() override;
|
||||
void ClearExclusiveState() override;
|
||||
|
|
@ -63,8 +61,12 @@ private:
|
|||
std::shared_ptr<Dynarmic::A64::Jit> MakeJit(Common::PageTable& page_table,
|
||||
std::size_t address_space_bits) const;
|
||||
|
||||
friend class ARM_Dynarmic_Callbacks;
|
||||
std::unique_ptr<ARM_Dynarmic_Callbacks> cb;
|
||||
using JitCacheKey = std::pair<Common::PageTable*, std::size_t>;
|
||||
using JitCacheType =
|
||||
std::unordered_map<JitCacheKey, std::shared_ptr<Dynarmic::A64::Jit>, Common::PairHash>;
|
||||
|
||||
friend class DynarmicCallbacks64;
|
||||
std::unique_ptr<DynarmicCallbacks64> cb;
|
||||
JitCacheType jit_cache;
|
||||
std::shared_ptr<Dynarmic::A64::Jit> jit;
|
||||
ARM_Unicorn inner_unicorn;
|
||||
|
|
@ -75,7 +77,7 @@ private:
|
|||
|
||||
class DynarmicExclusiveMonitor final : public ExclusiveMonitor {
|
||||
public:
|
||||
explicit DynarmicExclusiveMonitor(Memory::Memory& memory_, std::size_t core_count);
|
||||
explicit DynarmicExclusiveMonitor(Memory::Memory& memory, std::size_t core_count);
|
||||
~DynarmicExclusiveMonitor() override;
|
||||
|
||||
void SetExclusive(std::size_t core_index, VAddr addr) override;
|
||||
|
|
@ -88,7 +90,7 @@ public:
|
|||
bool ExclusiveWrite128(std::size_t core_index, VAddr vaddr, u128 value) override;
|
||||
|
||||
private:
|
||||
friend class ARM_Dynarmic;
|
||||
friend class ARM_Dynarmic_64;
|
||||
Dynarmic::A64::ExclusiveMonitor monitor;
|
||||
Memory::Memory& memory;
|
||||
};
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
// Refer to the license.txt file included.
|
||||
|
||||
#ifdef ARCHITECTURE_x86_64
|
||||
#include "core/arm/dynarmic/arm_dynarmic.h"
|
||||
#include "core/arm/dynarmic/arm_dynarmic_64.h"
|
||||
#endif
|
||||
#include "core/arm/exclusive_monitor.h"
|
||||
#include "core/memory.h"
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ static bool UnmappedMemoryHook(uc_engine* uc, uc_mem_type type, u64 addr, int si
|
|||
void* user_data) {
|
||||
auto* const system = static_cast<System*>(user_data);
|
||||
|
||||
ARM_Interface::ThreadContext ctx{};
|
||||
ARM_Interface::ThreadContext64 ctx{};
|
||||
system->CurrentArmInterface().SaveContext(ctx);
|
||||
ASSERT_MSG(false, "Attempted to read from unmapped memory: 0x{:X}, pc=0x{:X}, lr=0x{:X}", addr,
|
||||
ctx.pc, ctx.cpu_registers[30]);
|
||||
|
|
@ -179,7 +179,7 @@ void ARM_Unicorn::ExecuteInstructions(std::size_t num_instructions) {
|
|||
}
|
||||
|
||||
Kernel::Thread* const thread = system.CurrentScheduler().GetCurrentThread();
|
||||
SaveContext(thread->GetContext());
|
||||
SaveContext(thread->GetContext64());
|
||||
if (last_bkpt_hit || GDBStub::IsMemoryBreak() || GDBStub::GetCpuStepFlag()) {
|
||||
last_bkpt_hit = false;
|
||||
GDBStub::Break();
|
||||
|
|
@ -188,7 +188,7 @@ void ARM_Unicorn::ExecuteInstructions(std::size_t num_instructions) {
|
|||
}
|
||||
}
|
||||
|
||||
void ARM_Unicorn::SaveContext(ThreadContext& ctx) {
|
||||
void ARM_Unicorn::SaveContext(ThreadContext64& ctx) {
|
||||
int uregs[32];
|
||||
void* tregs[32];
|
||||
|
||||
|
|
@ -215,7 +215,7 @@ void ARM_Unicorn::SaveContext(ThreadContext& ctx) {
|
|||
CHECKED(uc_reg_read_batch(uc, uregs, tregs, 32));
|
||||
}
|
||||
|
||||
void ARM_Unicorn::LoadContext(const ThreadContext& ctx) {
|
||||
void ARM_Unicorn::LoadContext(const ThreadContext64& ctx) {
|
||||
int uregs[32];
|
||||
void* tregs[32];
|
||||
|
||||
|
|
|
|||
|
|
@ -30,8 +30,6 @@ public:
|
|||
void SetTlsAddress(VAddr address) override;
|
||||
void SetTPIDR_EL0(u64 value) override;
|
||||
u64 GetTPIDR_EL0() const override;
|
||||
void SaveContext(ThreadContext& ctx) override;
|
||||
void LoadContext(const ThreadContext& ctx) override;
|
||||
void PrepareReschedule() override;
|
||||
void ClearExclusiveState() override;
|
||||
void ExecuteInstructions(std::size_t num_instructions);
|
||||
|
|
@ -41,6 +39,11 @@ public:
|
|||
void PageTableChanged(Common::PageTable&, std::size_t) override {}
|
||||
void RecordBreak(GDBStub::BreakpointAddress bkpt);
|
||||
|
||||
void SaveContext(ThreadContext32& ctx) override {}
|
||||
void SaveContext(ThreadContext64& ctx) override;
|
||||
void LoadContext(const ThreadContext32& ctx) override {}
|
||||
void LoadContext(const ThreadContext64& ctx) override;
|
||||
|
||||
private:
|
||||
static void InterruptHook(uc_engine* uc, u32 int_no, void* user_data);
|
||||
|
||||
|
|
|
|||
|
|
@ -6,9 +6,6 @@
|
|||
#include <mutex>
|
||||
|
||||
#include "common/logging/log.h"
|
||||
#ifdef ARCHITECTURE_x86_64
|
||||
#include "core/arm/dynarmic/arm_dynarmic.h"
|
||||
#endif
|
||||
#include "core/arm/exclusive_monitor.h"
|
||||
#include "core/arm/unicorn/arm_unicorn.h"
|
||||
#include "core/core.h"
|
||||
|
|
|
|||
|
|
@ -217,7 +217,7 @@ static u64 RegRead(std::size_t id, Kernel::Thread* thread = nullptr) {
|
|||
return 0;
|
||||
}
|
||||
|
||||
const auto& thread_context = thread->GetContext();
|
||||
const auto& thread_context = thread->GetContext64();
|
||||
|
||||
if (id < SP_REGISTER) {
|
||||
return thread_context.cpu_registers[id];
|
||||
|
|
@ -239,7 +239,7 @@ static void RegWrite(std::size_t id, u64 val, Kernel::Thread* thread = nullptr)
|
|||
return;
|
||||
}
|
||||
|
||||
auto& thread_context = thread->GetContext();
|
||||
auto& thread_context = thread->GetContext64();
|
||||
|
||||
if (id < SP_REGISTER) {
|
||||
thread_context.cpu_registers[id] = val;
|
||||
|
|
@ -259,7 +259,7 @@ static u128 FpuRead(std::size_t id, Kernel::Thread* thread = nullptr) {
|
|||
return u128{0};
|
||||
}
|
||||
|
||||
auto& thread_context = thread->GetContext();
|
||||
auto& thread_context = thread->GetContext64();
|
||||
|
||||
if (id >= UC_ARM64_REG_Q0 && id < FPCR_REGISTER) {
|
||||
return thread_context.vector_registers[id - UC_ARM64_REG_Q0];
|
||||
|
|
@ -275,7 +275,7 @@ static void FpuWrite(std::size_t id, u128 val, Kernel::Thread* thread = nullptr)
|
|||
return;
|
||||
}
|
||||
|
||||
auto& thread_context = thread->GetContext();
|
||||
auto& thread_context = thread->GetContext64();
|
||||
|
||||
if (id >= UC_ARM64_REG_Q0 && id < FPCR_REGISTER) {
|
||||
thread_context.vector_registers[id - UC_ARM64_REG_Q0] = val;
|
||||
|
|
@ -916,7 +916,7 @@ static void WriteRegister() {
|
|||
// Update ARM context, skipping scheduler - no running threads at this point
|
||||
Core::System::GetInstance()
|
||||
.ArmInterface(current_core)
|
||||
.LoadContext(current_thread->GetContext());
|
||||
.LoadContext(current_thread->GetContext64());
|
||||
|
||||
SendReply("OK");
|
||||
}
|
||||
|
|
@ -947,7 +947,7 @@ static void WriteRegisters() {
|
|||
// Update ARM context, skipping scheduler - no running threads at this point
|
||||
Core::System::GetInstance()
|
||||
.ArmInterface(current_core)
|
||||
.LoadContext(current_thread->GetContext());
|
||||
.LoadContext(current_thread->GetContext64());
|
||||
|
||||
SendReply("OK");
|
||||
}
|
||||
|
|
@ -1019,7 +1019,7 @@ static void Step() {
|
|||
// Update ARM context, skipping scheduler - no running threads at this point
|
||||
Core::System::GetInstance()
|
||||
.ArmInterface(current_core)
|
||||
.LoadContext(current_thread->GetContext());
|
||||
.LoadContext(current_thread->GetContext64());
|
||||
}
|
||||
step_loop = true;
|
||||
halt_loop = true;
|
||||
|
|
|
|||
|
|
@ -186,6 +186,10 @@ struct KernelCore::Impl {
|
|||
return;
|
||||
}
|
||||
|
||||
for (auto& core : cores) {
|
||||
core.SetIs64Bit(process->Is64BitProcess());
|
||||
}
|
||||
|
||||
system.Memory().SetCurrentPageTable(*process);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,8 @@
|
|||
#include "common/logging/log.h"
|
||||
#include "core/arm/arm_interface.h"
|
||||
#ifdef ARCHITECTURE_x86_64
|
||||
#include "core/arm/dynarmic/arm_dynarmic.h"
|
||||
#include "core/arm/dynarmic/arm_dynarmic_32.h"
|
||||
#include "core/arm/dynarmic/arm_dynarmic_64.h"
|
||||
#endif
|
||||
#include "core/arm/exclusive_monitor.h"
|
||||
#include "core/arm/unicorn/arm_unicorn.h"
|
||||
|
|
@ -20,13 +21,17 @@ PhysicalCore::PhysicalCore(Core::System& system, std::size_t id,
|
|||
Core::ExclusiveMonitor& exclusive_monitor)
|
||||
: core_index{id} {
|
||||
#ifdef ARCHITECTURE_x86_64
|
||||
arm_interface = std::make_unique<Core::ARM_Dynarmic>(system, exclusive_monitor, core_index);
|
||||
arm_interface_32 =
|
||||
std::make_unique<Core::ARM_Dynarmic_32>(system, exclusive_monitor, core_index);
|
||||
arm_interface_64 =
|
||||
std::make_unique<Core::ARM_Dynarmic_64>(system, exclusive_monitor, core_index);
|
||||
|
||||
#else
|
||||
arm_interface = std::make_shared<Core::ARM_Unicorn>(system);
|
||||
LOG_WARNING(Core, "CPU JIT requested, but Dynarmic not available");
|
||||
#endif
|
||||
|
||||
scheduler = std::make_unique<Kernel::Scheduler>(system, *arm_interface, core_index);
|
||||
scheduler = std::make_unique<Kernel::Scheduler>(system, core_index);
|
||||
}
|
||||
|
||||
PhysicalCore::~PhysicalCore() = default;
|
||||
|
|
@ -48,4 +53,12 @@ void PhysicalCore::Shutdown() {
|
|||
scheduler->Shutdown();
|
||||
}
|
||||
|
||||
void PhysicalCore::SetIs64Bit(bool is_64_bit) {
|
||||
if (is_64_bit) {
|
||||
arm_interface = arm_interface_64.get();
|
||||
} else {
|
||||
arm_interface = arm_interface_32.get();
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace Kernel
|
||||
|
|
|
|||
|
|
@ -68,10 +68,14 @@ public:
|
|||
return *scheduler;
|
||||
}
|
||||
|
||||
void SetIs64Bit(bool is_64_bit);
|
||||
|
||||
private:
|
||||
std::size_t core_index;
|
||||
std::unique_ptr<Core::ARM_Interface> arm_interface;
|
||||
std::unique_ptr<Core::ARM_Interface> arm_interface_32;
|
||||
std::unique_ptr<Core::ARM_Interface> arm_interface_64;
|
||||
std::unique_ptr<Kernel::Scheduler> scheduler;
|
||||
Core::ARM_Interface* arm_interface{};
|
||||
};
|
||||
|
||||
} // namespace Kernel
|
||||
|
|
|
|||
|
|
@ -42,7 +42,8 @@ void SetupMainThread(Process& owner_process, KernelCore& kernel, u32 priority) {
|
|||
|
||||
// Register 1 must be a handle to the main thread
|
||||
const Handle thread_handle = owner_process.GetHandleTable().Create(thread).Unwrap();
|
||||
thread->GetContext().cpu_registers[1] = thread_handle;
|
||||
thread->GetContext32().cpu_registers[1] = thread_handle;
|
||||
thread->GetContext64().cpu_registers[1] = thread_handle;
|
||||
|
||||
// Threads by default are dormant, wake up the main thread so it runs when the scheduler fires
|
||||
thread->ResumeFromWait();
|
||||
|
|
|
|||
|
|
@ -383,8 +383,8 @@ void GlobalScheduler::Unlock() {
|
|||
// TODO(Blinkhawk): Setup the interrupts and change context on current core.
|
||||
}
|
||||
|
||||
Scheduler::Scheduler(Core::System& system, Core::ARM_Interface& cpu_core, std::size_t core_id)
|
||||
: system(system), cpu_core(cpu_core), core_id(core_id) {}
|
||||
Scheduler::Scheduler(Core::System& system, std::size_t core_id)
|
||||
: system{system}, core_id{core_id} {}
|
||||
|
||||
Scheduler::~Scheduler() = default;
|
||||
|
||||
|
|
@ -422,9 +422,10 @@ void Scheduler::UnloadThread() {
|
|||
|
||||
// Save context for previous thread
|
||||
if (previous_thread) {
|
||||
cpu_core.SaveContext(previous_thread->GetContext());
|
||||
system.ArmInterface(core_id).SaveContext(previous_thread->GetContext32());
|
||||
system.ArmInterface(core_id).SaveContext(previous_thread->GetContext64());
|
||||
// Save the TPIDR_EL0 system register in case it was modified.
|
||||
previous_thread->SetTPIDR_EL0(cpu_core.GetTPIDR_EL0());
|
||||
previous_thread->SetTPIDR_EL0(system.ArmInterface(core_id).GetTPIDR_EL0());
|
||||
|
||||
if (previous_thread->GetStatus() == ThreadStatus::Running) {
|
||||
// This is only the case when a reschedule is triggered without the current thread
|
||||
|
|
@ -451,9 +452,10 @@ void Scheduler::SwitchContext() {
|
|||
|
||||
// Save context for previous thread
|
||||
if (previous_thread) {
|
||||
cpu_core.SaveContext(previous_thread->GetContext());
|
||||
system.ArmInterface(core_id).SaveContext(previous_thread->GetContext32());
|
||||
system.ArmInterface(core_id).SaveContext(previous_thread->GetContext64());
|
||||
// Save the TPIDR_EL0 system register in case it was modified.
|
||||
previous_thread->SetTPIDR_EL0(cpu_core.GetTPIDR_EL0());
|
||||
previous_thread->SetTPIDR_EL0(system.ArmInterface(core_id).GetTPIDR_EL0());
|
||||
|
||||
if (previous_thread->GetStatus() == ThreadStatus::Running) {
|
||||
// This is only the case when a reschedule is triggered without the current thread
|
||||
|
|
@ -481,9 +483,10 @@ void Scheduler::SwitchContext() {
|
|||
system.Kernel().MakeCurrentProcess(thread_owner_process);
|
||||
}
|
||||
|
||||
cpu_core.LoadContext(new_thread->GetContext());
|
||||
cpu_core.SetTlsAddress(new_thread->GetTLSAddress());
|
||||
cpu_core.SetTPIDR_EL0(new_thread->GetTPIDR_EL0());
|
||||
system.ArmInterface(core_id).LoadContext(new_thread->GetContext32());
|
||||
system.ArmInterface(core_id).LoadContext(new_thread->GetContext64());
|
||||
system.ArmInterface(core_id).SetTlsAddress(new_thread->GetTLSAddress());
|
||||
system.ArmInterface(core_id).SetTPIDR_EL0(new_thread->GetTPIDR_EL0());
|
||||
} else {
|
||||
current_thread = nullptr;
|
||||
// Note: We do not reset the current process and current page table when idling because
|
||||
|
|
|
|||
|
|
@ -181,7 +181,7 @@ private:
|
|||
|
||||
class Scheduler final {
|
||||
public:
|
||||
explicit Scheduler(Core::System& system, Core::ARM_Interface& cpu_core, std::size_t core_id);
|
||||
explicit Scheduler(Core::System& system, std::size_t core_id);
|
||||
~Scheduler();
|
||||
|
||||
/// Returns whether there are any threads that are ready to run.
|
||||
|
|
@ -235,7 +235,6 @@ private:
|
|||
std::shared_ptr<Thread> selected_thread = nullptr;
|
||||
|
||||
Core::System& system;
|
||||
Core::ARM_Interface& cpu_core;
|
||||
u64 last_context_switch_time = 0;
|
||||
u64 idle_selection_count = 0;
|
||||
const std::size_t core_id;
|
||||
|
|
|
|||
|
|
@ -133,14 +133,15 @@ void Thread::CancelWait() {
|
|||
ResumeFromWait();
|
||||
}
|
||||
|
||||
/**
|
||||
* Resets a thread context, making it ready to be scheduled and run by the CPU
|
||||
* @param context Thread context to reset
|
||||
* @param stack_top Address of the top of the stack
|
||||
* @param entry_point Address of entry point for execution
|
||||
* @param arg User argument for thread
|
||||
*/
|
||||
static void ResetThreadContext(Core::ARM_Interface::ThreadContext& context, VAddr stack_top,
|
||||
static void ResetThreadContext32(Core::ARM_Interface::ThreadContext32& context, u32 stack_top,
|
||||
u32 entry_point, u32 arg) {
|
||||
context = {};
|
||||
context.cpu_registers[0] = arg;
|
||||
context.cpu_registers[15] = entry_point;
|
||||
context.cpu_registers[13] = stack_top;
|
||||
}
|
||||
|
||||
static void ResetThreadContext64(Core::ARM_Interface::ThreadContext64& context, VAddr stack_top,
|
||||
VAddr entry_point, u64 arg) {
|
||||
context = {};
|
||||
context.cpu_registers[0] = arg;
|
||||
|
|
@ -198,9 +199,9 @@ ResultVal<std::shared_ptr<Thread>> Thread::Create(KernelCore& kernel, std::strin
|
|||
|
||||
thread->owner_process->RegisterThread(thread.get());
|
||||
|
||||
// TODO(peachum): move to ScheduleThread() when scheduler is added so selected core is used
|
||||
// to initialize the context
|
||||
ResetThreadContext(thread->context, stack_top, entry_point, arg);
|
||||
ResetThreadContext32(thread->context_32, static_cast<u32>(stack_top),
|
||||
static_cast<u32>(entry_point), static_cast<u32>(arg));
|
||||
ResetThreadContext64(thread->context_64, stack_top, entry_point, arg);
|
||||
|
||||
return MakeResult<std::shared_ptr<Thread>>(std::move(thread));
|
||||
}
|
||||
|
|
@ -213,11 +214,13 @@ void Thread::SetPriority(u32 priority) {
|
|||
}
|
||||
|
||||
void Thread::SetWaitSynchronizationResult(ResultCode result) {
|
||||
context.cpu_registers[0] = result.raw;
|
||||
context_32.cpu_registers[0] = result.raw;
|
||||
context_64.cpu_registers[0] = result.raw;
|
||||
}
|
||||
|
||||
void Thread::SetWaitSynchronizationOutput(s32 output) {
|
||||
context.cpu_registers[1] = output;
|
||||
context_32.cpu_registers[1] = output;
|
||||
context_64.cpu_registers[1] = output;
|
||||
}
|
||||
|
||||
s32 Thread::GetSynchronizationObjectIndex(std::shared_ptr<SynchronizationObject> object) const {
|
||||
|
|
|
|||
|
|
@ -102,7 +102,8 @@ public:
|
|||
|
||||
using MutexWaitingThreads = std::vector<std::shared_ptr<Thread>>;
|
||||
|
||||
using ThreadContext = Core::ARM_Interface::ThreadContext;
|
||||
using ThreadContext32 = Core::ARM_Interface::ThreadContext32;
|
||||
using ThreadContext64 = Core::ARM_Interface::ThreadContext64;
|
||||
|
||||
using ThreadSynchronizationObjects = std::vector<std::shared_ptr<SynchronizationObject>>;
|
||||
|
||||
|
|
@ -273,12 +274,20 @@ public:
|
|||
return status == ThreadStatus::WaitSynch;
|
||||
}
|
||||
|
||||
ThreadContext& GetContext() {
|
||||
return context;
|
||||
ThreadContext32& GetContext32() {
|
||||
return context_32;
|
||||
}
|
||||
|
||||
const ThreadContext& GetContext() const {
|
||||
return context;
|
||||
const ThreadContext32& GetContext32() const {
|
||||
return context_32;
|
||||
}
|
||||
|
||||
ThreadContext64& GetContext64() {
|
||||
return context_64;
|
||||
}
|
||||
|
||||
const ThreadContext64& GetContext64() const {
|
||||
return context_64;
|
||||
}
|
||||
|
||||
ThreadStatus GetStatus() const {
|
||||
|
|
@ -466,7 +475,8 @@ private:
|
|||
void AdjustSchedulingOnPriority(u32 old_priority);
|
||||
void AdjustSchedulingOnAffinity(u64 old_affinity_mask, s32 old_core);
|
||||
|
||||
Core::ARM_Interface::ThreadContext context{};
|
||||
ThreadContext32 context_32{};
|
||||
ThreadContext64 context_64{};
|
||||
|
||||
u64 thread_id = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@ json GetProcessorStateDataAuto(Core::System& system) {
|
|||
const auto& vm_manager{process->VMManager()};
|
||||
auto& arm{system.CurrentArmInterface()};
|
||||
|
||||
Core::ARM_Interface::ThreadContext context{};
|
||||
Core::ARM_Interface::ThreadContext64 context{};
|
||||
arm.SaveContext(context);
|
||||
|
||||
return GetProcessorStateData(process->Is64BitProcess() ? "AArch64" : "AArch32",
|
||||
|
|
|
|||
|
|
@ -116,7 +116,7 @@ std::vector<std::unique_ptr<WaitTreeItem>> WaitTreeCallstack::GetChildren() cons
|
|||
|
||||
constexpr std::size_t BaseRegister = 29;
|
||||
auto& memory = Core::System::GetInstance().Memory();
|
||||
u64 base_pointer = thread.GetContext().cpu_registers[BaseRegister];
|
||||
u64 base_pointer = thread.GetContext64().cpu_registers[BaseRegister];
|
||||
|
||||
while (base_pointer != 0) {
|
||||
const u64 lr = memory.Read64(base_pointer + sizeof(u64));
|
||||
|
|
@ -240,7 +240,7 @@ QString WaitTreeThread::GetText() const {
|
|||
break;
|
||||
}
|
||||
|
||||
const auto& context = thread.GetContext();
|
||||
const auto& context = thread.GetContext64();
|
||||
const QString pc_info = tr(" PC = 0x%1 LR = 0x%2")
|
||||
.arg(context.pc, 8, 16, QLatin1Char{'0'})
|
||||
.arg(context.cpu_registers[30], 8, 16, QLatin1Char{'0'});
|
||||
|
|
|
|||
Loading…
Reference in a new issue