shaders: Add U64->U32x2 Atomic fallback functions
This commit is contained in:
ameerj
parent
11099dda2e
commit
ad58d7eae7
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@ -372,6 +372,8 @@ void EmitSharedAtomicExchange32(EmitContext& ctx, IR::Inst& inst, ScalarU32 poin
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ScalarU32 value);
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void EmitSharedAtomicExchange64(EmitContext& ctx, IR::Inst& inst, ScalarU32 pointer_offset,
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Register value);
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void EmitSharedAtomicExchange32x2(EmitContext& ctx, IR::Inst& inst, ScalarU32 pointer_offset,
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Register value);
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void EmitStorageAtomicIAdd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, ScalarU32 value);
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void EmitStorageAtomicSMin32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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@ -412,6 +414,24 @@ void EmitStorageAtomicXor64(EmitContext& ctx, IR::Inst& inst, const IR::Value& b
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ScalarU32 offset, Register value);
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void EmitStorageAtomicExchange64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicIAdd32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicSMin32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicUMin32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicSMax32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicUMax32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicAnd32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicOr32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicXor32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicExchange32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicAddF32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, ScalarF32 value);
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void EmitStorageAtomicAddF16x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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@ -448,6 +468,17 @@ void EmitGlobalAtomicAnd64(EmitContext& ctx);
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void EmitGlobalAtomicOr64(EmitContext& ctx);
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void EmitGlobalAtomicXor64(EmitContext& ctx);
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void EmitGlobalAtomicExchange64(EmitContext& ctx);
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void EmitGlobalAtomicIAdd32x2(EmitContext& ctx);
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void EmitGlobalAtomicSMin32x2(EmitContext& ctx);
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void EmitGlobalAtomicUMin32x2(EmitContext& ctx);
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void EmitGlobalAtomicSMax32x2(EmitContext& ctx);
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void EmitGlobalAtomicUMax32x2(EmitContext& ctx);
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void EmitGlobalAtomicInc32x2(EmitContext& ctx);
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void EmitGlobalAtomicDec32x2(EmitContext& ctx);
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void EmitGlobalAtomicAnd32x2(EmitContext& ctx);
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void EmitGlobalAtomicOr32x2(EmitContext& ctx);
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void EmitGlobalAtomicXor32x2(EmitContext& ctx);
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void EmitGlobalAtomicExchange32x2(EmitContext& ctx);
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void EmitGlobalAtomicAddF32(EmitContext& ctx);
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void EmitGlobalAtomicAddF16x2(EmitContext& ctx);
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void EmitGlobalAtomicAddF32x2(EmitContext& ctx);
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@ -311,6 +311,13 @@ void EmitSharedAtomicExchange64(EmitContext& ctx, IR::Inst& inst, ScalarU32 poin
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ctx.LongAdd("ATOMS.EXCH.U64 {}.x,{},shared_mem[{}];", inst, value, pointer_offset);
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}
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void EmitSharedAtomicExchange32x2([[maybe_unused]] EmitContext& ctx,
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[[maybe_unused]] IR::Inst& inst,
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[[maybe_unused]] ScalarU32 pointer_offset,
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[[maybe_unused]] Register value) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitStorageAtomicIAdd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, ScalarU32 value) {
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Atom(ctx, inst, binding, offset, value, "ADD", "U32");
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@ -411,6 +418,62 @@ void EmitStorageAtomicExchange64(EmitContext& ctx, IR::Inst& inst, const IR::Val
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Atom(ctx, inst, binding, offset, value, "EXCH", "U64");
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}
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void EmitStorageAtomicIAdd32x2([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] IR::Inst& inst,
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[[maybe_unused]] const IR::Value& binding,
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[[maybe_unused]] ScalarU32 offset, [[maybe_unused]] Register value) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitStorageAtomicSMin32x2([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] IR::Inst& inst,
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[[maybe_unused]] const IR::Value& binding,
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[[maybe_unused]] ScalarU32 offset, [[maybe_unused]] Register value) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitStorageAtomicUMin32x2([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] IR::Inst& inst,
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[[maybe_unused]] const IR::Value& binding,
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[[maybe_unused]] ScalarU32 offset, [[maybe_unused]] Register value) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitStorageAtomicSMax32x2([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] IR::Inst& inst,
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[[maybe_unused]] const IR::Value& binding,
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[[maybe_unused]] ScalarU32 offset, [[maybe_unused]] Register value) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitStorageAtomicUMax32x2([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] IR::Inst& inst,
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[[maybe_unused]] const IR::Value& binding,
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[[maybe_unused]] ScalarU32 offset, [[maybe_unused]] Register value) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitStorageAtomicAnd32x2([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] IR::Inst& inst,
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[[maybe_unused]] const IR::Value& binding,
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[[maybe_unused]] ScalarU32 offset, [[maybe_unused]] Register value) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitStorageAtomicOr32x2([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] IR::Inst& inst,
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[[maybe_unused]] const IR::Value& binding,
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[[maybe_unused]] ScalarU32 offset, [[maybe_unused]] Register value) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitStorageAtomicXor32x2([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] IR::Inst& inst,
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[[maybe_unused]] const IR::Value& binding,
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[[maybe_unused]] ScalarU32 offset, [[maybe_unused]] Register value) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitStorageAtomicExchange32x2([[maybe_unused]] EmitContext& ctx,
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[[maybe_unused]] IR::Inst& inst,
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[[maybe_unused]] const IR::Value& binding,
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[[maybe_unused]] ScalarU32 offset,
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[[maybe_unused]] Register value) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitStorageAtomicAddF32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, ScalarF32 value) {
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Atom(ctx, inst, binding, offset, value, "ADD", "F32");
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@ -537,6 +600,50 @@ void EmitGlobalAtomicExchange64(EmitContext&) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitGlobalAtomicIAdd32x2(EmitContext&) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitGlobalAtomicSMin32x2(EmitContext&) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitGlobalAtomicUMin32x2(EmitContext&) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitGlobalAtomicSMax32x2(EmitContext&) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitGlobalAtomicUMax32x2(EmitContext&) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitGlobalAtomicInc32x2(EmitContext&) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitGlobalAtomicDec32x2(EmitContext&) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitGlobalAtomicAnd32x2(EmitContext&) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitGlobalAtomicOr32x2(EmitContext&) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitGlobalAtomicXor32x2(EmitContext&) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitGlobalAtomicExchange32x2(EmitContext&) {
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throw NotImplementedException("GLASM instruction");
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}
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void EmitGlobalAtomicAddF32(EmitContext&) {
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throw NotImplementedException("GLASM instruction");
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}
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@ -105,6 +105,13 @@ void EmitSharedAtomicExchange64(EmitContext& ctx, IR::Inst& inst, std::string_vi
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pointer_offset, value, pointer_offset, value);
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}
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void EmitSharedAtomicExchange32x2(EmitContext& ctx, IR::Inst& inst, std::string_view pointer_offset,
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std::string_view value) {
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LOG_WARNING(Shader_GLSL, "Int64 atomics not supported, fallback to non-atomic");
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ctx.AddU32x2("{}=uvec2(smem[{}>>2],smem[({}+4)>>2]);", inst, pointer_offset, pointer_offset);
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ctx.Add("smem[{}>>2]={}.x;smem[({}+4)>>2]={}.y;", pointer_offset, value, pointer_offset, value);
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}
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void EmitStorageAtomicIAdd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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ctx.AddU32("{}=atomicAdd({}_ssbo{}[{}>>2],{});", inst, ctx.stage_name, binding.U32(),
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@ -265,6 +272,51 @@ void EmitStorageAtomicExchange64(EmitContext& ctx, IR::Inst& inst, const IR::Val
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ctx.stage_name, binding.U32(), ctx.var_alloc.Consume(offset), value);
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}
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void EmitStorageAtomicIAdd32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitStorageAtomicSMin32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitStorageAtomicUMin32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitStorageAtomicSMax32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitStorageAtomicUMax32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitStorageAtomicAnd32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitStorageAtomicOr32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitStorageAtomicXor32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitStorageAtomicExchange32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitStorageAtomicAddF32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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SsboCasFunctionF32(ctx, inst, binding, offset, value, "CasFloatAdd");
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@ -388,6 +440,50 @@ void EmitGlobalAtomicExchange64(EmitContext&) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitGlobalAtomicIAdd32x2(EmitContext&) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitGlobalAtomicSMin32x2(EmitContext&) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitGlobalAtomicUMin32x2(EmitContext&) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitGlobalAtomicSMax32x2(EmitContext&) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitGlobalAtomicUMax32x2(EmitContext&) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitGlobalAtomicInc32x2(EmitContext&) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitGlobalAtomicDec32x2(EmitContext&) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitGlobalAtomicAnd32x2(EmitContext&) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitGlobalAtomicOr32x2(EmitContext&) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitGlobalAtomicXor32x2(EmitContext&) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitGlobalAtomicExchange32x2(EmitContext&) {
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throw NotImplementedException("GLSL Instrucion");
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}
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void EmitGlobalAtomicAddF32(EmitContext&) {
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throw NotImplementedException("GLSL Instrucion");
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}
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@ -442,6 +442,8 @@ void EmitSharedAtomicExchange32(EmitContext& ctx, IR::Inst& inst, std::string_vi
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std::string_view value);
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void EmitSharedAtomicExchange64(EmitContext& ctx, IR::Inst& inst, std::string_view pointer_offset,
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std::string_view value);
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void EmitSharedAtomicExchange32x2(EmitContext& ctx, IR::Inst& inst, std::string_view pointer_offset,
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std::string_view value);
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void EmitStorageAtomicIAdd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value);
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void EmitStorageAtomicSMin32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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@ -482,6 +484,24 @@ void EmitStorageAtomicXor64(EmitContext& ctx, IR::Inst& inst, const IR::Value& b
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const IR::Value& offset, std::string_view value);
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void EmitStorageAtomicExchange64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value);
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void EmitStorageAtomicIAdd32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value);
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void EmitStorageAtomicSMin32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value);
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void EmitStorageAtomicUMin32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value);
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void EmitStorageAtomicSMax32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value);
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void EmitStorageAtomicUMax32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value);
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void EmitStorageAtomicAnd32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value);
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void EmitStorageAtomicOr32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value);
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void EmitStorageAtomicXor32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value);
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void EmitStorageAtomicExchange32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value);
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void EmitStorageAtomicAddF32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value);
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void EmitStorageAtomicAddF16x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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@ -518,6 +538,17 @@ void EmitGlobalAtomicAnd64(EmitContext& ctx);
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void EmitGlobalAtomicOr64(EmitContext& ctx);
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void EmitGlobalAtomicXor64(EmitContext& ctx);
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void EmitGlobalAtomicExchange64(EmitContext& ctx);
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void EmitGlobalAtomicIAdd32x2(EmitContext& ctx);
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void EmitGlobalAtomicSMin32x2(EmitContext& ctx);
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void EmitGlobalAtomicUMin32x2(EmitContext& ctx);
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void EmitGlobalAtomicSMax32x2(EmitContext& ctx);
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void EmitGlobalAtomicUMax32x2(EmitContext& ctx);
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void EmitGlobalAtomicInc32x2(EmitContext& ctx);
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void EmitGlobalAtomicDec32x2(EmitContext& ctx);
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void EmitGlobalAtomicAnd32x2(EmitContext& ctx);
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void EmitGlobalAtomicOr32x2(EmitContext& ctx);
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void EmitGlobalAtomicXor32x2(EmitContext& ctx);
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void EmitGlobalAtomicExchange32x2(EmitContext& ctx);
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void EmitGlobalAtomicAddF32(EmitContext& ctx);
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void EmitGlobalAtomicAddF16x2(EmitContext& ctx);
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void EmitGlobalAtomicAddF32x2(EmitContext& ctx);
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@ -82,6 +82,17 @@ Id StorageAtomicU64(EmitContext& ctx, const IR::Value& binding, const IR::Value&
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ctx.OpStore(pointer, ctx.OpBitcast(ctx.U32[2], result));
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return original_value;
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}
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|
||||
Id StorageAtomicU32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, Id value,
|
||||
Id (Sirit::Module::*non_atomic_func)(Id, Id, Id)) {
|
||||
LOG_WARNING(Shader_SPIRV, "Int64 atomics not supported, fallback to non-atomic");
|
||||
const Id pointer{StoragePointer(ctx, ctx.storage_types.U32x2, &StorageDefinitions::U32x2,
|
||||
binding, offset, sizeof(u32[2]))};
|
||||
const Id original_value{ctx.OpLoad(ctx.U32[2], pointer)};
|
||||
const Id result{(ctx.*non_atomic_func)(ctx.U32[2], value, original_value)};
|
||||
ctx.OpStore(pointer, result);
|
||||
return original_value;
|
||||
}
|
||||
} // Anonymous namespace
|
||||
|
||||
Id EmitSharedAtomicIAdd32(EmitContext& ctx, Id offset, Id value) {
|
||||
|
|
@ -141,7 +152,7 @@ Id EmitSharedAtomicExchange64(EmitContext& ctx, Id offset, Id value) {
|
|||
const auto [scope, semantics]{AtomicArgs(ctx)};
|
||||
return ctx.OpAtomicExchange(ctx.U64, pointer, scope, semantics, value);
|
||||
}
|
||||
LOG_ERROR(Shader_SPIRV, "Int64 atomics not supported, fallback to non-atomic");
|
||||
LOG_WARNING(Shader_SPIRV, "Int64 atomics not supported, fallback to non-atomic");
|
||||
const Id pointer_1{SharedPointer(ctx, offset, 0)};
|
||||
const Id pointer_2{SharedPointer(ctx, offset, 1)};
|
||||
const Id value_1{ctx.OpLoad(ctx.U32[1], pointer_1)};
|
||||
|
|
@ -152,6 +163,18 @@ Id EmitSharedAtomicExchange64(EmitContext& ctx, Id offset, Id value) {
|
|||
return ctx.OpBitcast(ctx.U64, ctx.OpCompositeConstruct(ctx.U32[2], value_1, value_2));
|
||||
}
|
||||
|
||||
Id EmitSharedAtomicExchange32x2(EmitContext& ctx, Id offset, Id value) {
|
||||
LOG_WARNING(Shader_SPIRV, "Int64 atomics not supported, fallback to non-atomic");
|
||||
const Id pointer_1{SharedPointer(ctx, offset, 0)};
|
||||
const Id pointer_2{SharedPointer(ctx, offset, 1)};
|
||||
const Id value_1{ctx.OpLoad(ctx.U32[1], pointer_1)};
|
||||
const Id value_2{ctx.OpLoad(ctx.U32[1], pointer_2)};
|
||||
const Id new_vector{ctx.OpBitcast(ctx.U32[2], value)};
|
||||
ctx.OpStore(pointer_1, ctx.OpCompositeExtract(ctx.U32[1], new_vector, 0U));
|
||||
ctx.OpStore(pointer_2, ctx.OpCompositeExtract(ctx.U32[1], new_vector, 1U));
|
||||
return ctx.OpCompositeConstruct(ctx.U32[2], value_1, value_2);
|
||||
}
|
||||
|
||||
Id EmitStorageAtomicIAdd32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value) {
|
||||
return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicIAdd);
|
||||
|
|
@ -275,6 +298,56 @@ Id EmitStorageAtomicExchange64(EmitContext& ctx, const IR::Value& binding, const
|
|||
return original;
|
||||
}
|
||||
|
||||
Id EmitStorageAtomicIAdd32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value) {
|
||||
return StorageAtomicU32x2(ctx, binding, offset, value, &Sirit::Module::OpIAdd);
|
||||
}
|
||||
|
||||
Id EmitStorageAtomicSMin32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value) {
|
||||
return StorageAtomicU32x2(ctx, binding, offset, value, &Sirit::Module::OpSMin);
|
||||
}
|
||||
|
||||
Id EmitStorageAtomicUMin32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value) {
|
||||
return StorageAtomicU32x2(ctx, binding, offset, value, &Sirit::Module::OpUMin);
|
||||
}
|
||||
|
||||
Id EmitStorageAtomicSMax32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value) {
|
||||
return StorageAtomicU32x2(ctx, binding, offset, value, &Sirit::Module::OpSMax);
|
||||
}
|
||||
|
||||
Id EmitStorageAtomicUMax32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value) {
|
||||
return StorageAtomicU32x2(ctx, binding, offset, value, &Sirit::Module::OpUMax);
|
||||
}
|
||||
|
||||
Id EmitStorageAtomicAnd32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value) {
|
||||
return StorageAtomicU32x2(ctx, binding, offset, value, &Sirit::Module::OpBitwiseAnd);
|
||||
}
|
||||
|
||||
Id EmitStorageAtomicOr32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value) {
|
||||
return StorageAtomicU32x2(ctx, binding, offset, value, &Sirit::Module::OpBitwiseOr);
|
||||
}
|
||||
|
||||
Id EmitStorageAtomicXor32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value) {
|
||||
return StorageAtomicU32x2(ctx, binding, offset, value, &Sirit::Module::OpBitwiseXor);
|
||||
}
|
||||
|
||||
Id EmitStorageAtomicExchange32x2(EmitContext& ctx, const IR::Value& binding,
|
||||
const IR::Value& offset, Id value) {
|
||||
LOG_WARNING(Shader_SPIRV, "Int64 atomics not supported, fallback to non-atomic");
|
||||
const Id pointer{StoragePointer(ctx, ctx.storage_types.U32x2, &StorageDefinitions::U32x2,
|
||||
binding, offset, sizeof(u32[2]))};
|
||||
const Id original{ctx.OpLoad(ctx.U32[2], pointer)};
|
||||
ctx.OpStore(pointer, value);
|
||||
return original;
|
||||
}
|
||||
|
||||
Id EmitStorageAtomicAddF32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value) {
|
||||
const Id ssbo{ctx.ssbos[binding.U32()].U32};
|
||||
|
|
@ -418,6 +491,50 @@ Id EmitGlobalAtomicExchange64(EmitContext&) {
|
|||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
Id EmitGlobalAtomicIAdd32x2(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
Id EmitGlobalAtomicSMin32x2(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
Id EmitGlobalAtomicUMin32x2(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
Id EmitGlobalAtomicSMax32x2(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
Id EmitGlobalAtomicUMax32x2(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
Id EmitGlobalAtomicInc32x2(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
Id EmitGlobalAtomicDec32x2(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
Id EmitGlobalAtomicAnd32x2(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
Id EmitGlobalAtomicOr32x2(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
Id EmitGlobalAtomicXor32x2(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
Id EmitGlobalAtomicExchange32x2(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
Id EmitGlobalAtomicAddF32(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -335,6 +335,7 @@ Id EmitSharedAtomicOr32(EmitContext& ctx, Id pointer_offset, Id value);
|
|||
Id EmitSharedAtomicXor32(EmitContext& ctx, Id pointer_offset, Id value);
|
||||
Id EmitSharedAtomicExchange32(EmitContext& ctx, Id pointer_offset, Id value);
|
||||
Id EmitSharedAtomicExchange64(EmitContext& ctx, Id pointer_offset, Id value);
|
||||
Id EmitSharedAtomicExchange32x2(EmitContext& ctx, Id pointer_offset, Id value);
|
||||
Id EmitStorageAtomicIAdd32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value);
|
||||
Id EmitStorageAtomicSMin32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
|
|
@ -375,6 +376,24 @@ Id EmitStorageAtomicXor64(EmitContext& ctx, const IR::Value& binding, const IR::
|
|||
Id value);
|
||||
Id EmitStorageAtomicExchange64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value);
|
||||
Id EmitStorageAtomicIAdd32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value);
|
||||
Id EmitStorageAtomicSMin32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value);
|
||||
Id EmitStorageAtomicUMin32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value);
|
||||
Id EmitStorageAtomicSMax32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value);
|
||||
Id EmitStorageAtomicUMax32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value);
|
||||
Id EmitStorageAtomicAnd32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value);
|
||||
Id EmitStorageAtomicOr32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value);
|
||||
Id EmitStorageAtomicXor32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value);
|
||||
Id EmitStorageAtomicExchange32x2(EmitContext& ctx, const IR::Value& binding,
|
||||
const IR::Value& offset, Id value);
|
||||
Id EmitStorageAtomicAddF32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value);
|
||||
Id EmitStorageAtomicAddF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
|
|
@ -411,6 +430,17 @@ Id EmitGlobalAtomicAnd64(EmitContext& ctx);
|
|||
Id EmitGlobalAtomicOr64(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicXor64(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicExchange64(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicIAdd32x2(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicSMin32x2(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicUMin32x2(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicSMax32x2(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicUMax32x2(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicInc32x2(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicDec32x2(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicAnd32x2(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicOr32x2(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicXor32x2(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicExchange32x2(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicAddF32(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicAddF16x2(EmitContext& ctx);
|
||||
Id EmitGlobalAtomicAddF32x2(EmitContext& ctx);
|
||||
|
|
|
|||
|
|
@ -118,6 +118,7 @@ bool Inst::MayHaveSideEffects() const noexcept {
|
|||
case Opcode::SharedAtomicXor32:
|
||||
case Opcode::SharedAtomicExchange32:
|
||||
case Opcode::SharedAtomicExchange64:
|
||||
case Opcode::SharedAtomicExchange32x2:
|
||||
case Opcode::GlobalAtomicIAdd32:
|
||||
case Opcode::GlobalAtomicSMin32:
|
||||
case Opcode::GlobalAtomicUMin32:
|
||||
|
|
@ -138,6 +139,15 @@ bool Inst::MayHaveSideEffects() const noexcept {
|
|||
case Opcode::GlobalAtomicOr64:
|
||||
case Opcode::GlobalAtomicXor64:
|
||||
case Opcode::GlobalAtomicExchange64:
|
||||
case Opcode::GlobalAtomicIAdd32x2:
|
||||
case Opcode::GlobalAtomicSMin32x2:
|
||||
case Opcode::GlobalAtomicUMin32x2:
|
||||
case Opcode::GlobalAtomicSMax32x2:
|
||||
case Opcode::GlobalAtomicUMax32x2:
|
||||
case Opcode::GlobalAtomicAnd32x2:
|
||||
case Opcode::GlobalAtomicOr32x2:
|
||||
case Opcode::GlobalAtomicXor32x2:
|
||||
case Opcode::GlobalAtomicExchange32x2:
|
||||
case Opcode::GlobalAtomicAddF32:
|
||||
case Opcode::GlobalAtomicAddF16x2:
|
||||
case Opcode::GlobalAtomicAddF32x2:
|
||||
|
|
@ -165,6 +175,15 @@ bool Inst::MayHaveSideEffects() const noexcept {
|
|||
case Opcode::StorageAtomicOr64:
|
||||
case Opcode::StorageAtomicXor64:
|
||||
case Opcode::StorageAtomicExchange64:
|
||||
case Opcode::StorageAtomicIAdd32x2:
|
||||
case Opcode::StorageAtomicSMin32x2:
|
||||
case Opcode::StorageAtomicUMin32x2:
|
||||
case Opcode::StorageAtomicSMax32x2:
|
||||
case Opcode::StorageAtomicUMax32x2:
|
||||
case Opcode::StorageAtomicAnd32x2:
|
||||
case Opcode::StorageAtomicOr32x2:
|
||||
case Opcode::StorageAtomicXor32x2:
|
||||
case Opcode::StorageAtomicExchange32x2:
|
||||
case Opcode::StorageAtomicAddF32:
|
||||
case Opcode::StorageAtomicAddF16x2:
|
||||
case Opcode::StorageAtomicAddF32x2:
|
||||
|
|
|
|||
|
|
@ -341,6 +341,7 @@ OPCODE(SharedAtomicOr32, U32, U32,
|
|||
OPCODE(SharedAtomicXor32, U32, U32, U32, )
|
||||
OPCODE(SharedAtomicExchange32, U32, U32, U32, )
|
||||
OPCODE(SharedAtomicExchange64, U64, U32, U64, )
|
||||
OPCODE(SharedAtomicExchange32x2, U32x2, U32, U32x2, )
|
||||
|
||||
OPCODE(GlobalAtomicIAdd32, U32, U64, U32, )
|
||||
OPCODE(GlobalAtomicSMin32, U32, U64, U32, )
|
||||
|
|
@ -362,6 +363,15 @@ OPCODE(GlobalAtomicAnd64, U64, U64,
|
|||
OPCODE(GlobalAtomicOr64, U64, U64, U64, )
|
||||
OPCODE(GlobalAtomicXor64, U64, U64, U64, )
|
||||
OPCODE(GlobalAtomicExchange64, U64, U64, U64, )
|
||||
OPCODE(GlobalAtomicIAdd32x2, U32x2, U64, U32x2, )
|
||||
OPCODE(GlobalAtomicSMin32x2, U32x2, U64, U32x2, )
|
||||
OPCODE(GlobalAtomicUMin32x2, U32x2, U64, U32x2, )
|
||||
OPCODE(GlobalAtomicSMax32x2, U32x2, U64, U32x2, )
|
||||
OPCODE(GlobalAtomicUMax32x2, U32x2, U64, U32x2, )
|
||||
OPCODE(GlobalAtomicAnd32x2, U32x2, U64, U32x2, )
|
||||
OPCODE(GlobalAtomicOr32x2, U32x2, U64, U32x2, )
|
||||
OPCODE(GlobalAtomicXor32x2, U32x2, U64, U32x2, )
|
||||
OPCODE(GlobalAtomicExchange32x2, U32x2, U64, U32x2, )
|
||||
OPCODE(GlobalAtomicAddF32, F32, U64, F32, )
|
||||
OPCODE(GlobalAtomicAddF16x2, U32, U64, F16x2, )
|
||||
OPCODE(GlobalAtomicAddF32x2, U32, U64, F32x2, )
|
||||
|
|
@ -390,6 +400,15 @@ OPCODE(StorageAtomicAnd64, U64, U32,
|
|||
OPCODE(StorageAtomicOr64, U64, U32, U32, U64, )
|
||||
OPCODE(StorageAtomicXor64, U64, U32, U32, U64, )
|
||||
OPCODE(StorageAtomicExchange64, U64, U32, U32, U64, )
|
||||
OPCODE(StorageAtomicIAdd32x2, U32x2, U32, U32, U32x2, )
|
||||
OPCODE(StorageAtomicSMin32x2, U32x2, U32, U32, U32x2, )
|
||||
OPCODE(StorageAtomicUMin32x2, U32x2, U32, U32, U32x2, )
|
||||
OPCODE(StorageAtomicSMax32x2, U32x2, U32, U32, U32x2, )
|
||||
OPCODE(StorageAtomicUMax32x2, U32x2, U32, U32, U32x2, )
|
||||
OPCODE(StorageAtomicAnd32x2, U32x2, U32, U32, U32x2, )
|
||||
OPCODE(StorageAtomicOr32x2, U32x2, U32, U32, U32x2, )
|
||||
OPCODE(StorageAtomicXor32x2, U32x2, U32, U32, U32x2, )
|
||||
OPCODE(StorageAtomicExchange32x2, U32x2, U32, U32, U32x2, )
|
||||
OPCODE(StorageAtomicAddF32, F32, U32, U32, F32, )
|
||||
OPCODE(StorageAtomicAddF16x2, U32, U32, U32, F16x2, )
|
||||
OPCODE(StorageAtomicAddF32x2, U32, U32, U32, F32x2, )
|
||||
|
|
|
|||
|
|
@ -360,6 +360,15 @@ void VisitUsages(Info& info, IR::Inst& inst) {
|
|||
case IR::Opcode::GlobalAtomicOr64:
|
||||
case IR::Opcode::GlobalAtomicXor64:
|
||||
case IR::Opcode::GlobalAtomicExchange64:
|
||||
case IR::Opcode::GlobalAtomicIAdd32x2:
|
||||
case IR::Opcode::GlobalAtomicSMin32x2:
|
||||
case IR::Opcode::GlobalAtomicUMin32x2:
|
||||
case IR::Opcode::GlobalAtomicSMax32x2:
|
||||
case IR::Opcode::GlobalAtomicUMax32x2:
|
||||
case IR::Opcode::GlobalAtomicAnd32x2:
|
||||
case IR::Opcode::GlobalAtomicOr32x2:
|
||||
case IR::Opcode::GlobalAtomicXor32x2:
|
||||
case IR::Opcode::GlobalAtomicExchange32x2:
|
||||
case IR::Opcode::GlobalAtomicAddF32:
|
||||
case IR::Opcode::GlobalAtomicAddF16x2:
|
||||
case IR::Opcode::GlobalAtomicAddF32x2:
|
||||
|
|
@ -597,6 +606,15 @@ void VisitUsages(Info& info, IR::Inst& inst) {
|
|||
break;
|
||||
case IR::Opcode::LoadStorage64:
|
||||
case IR::Opcode::WriteStorage64:
|
||||
case IR::Opcode::StorageAtomicIAdd32x2:
|
||||
case IR::Opcode::StorageAtomicSMin32x2:
|
||||
case IR::Opcode::StorageAtomicUMin32x2:
|
||||
case IR::Opcode::StorageAtomicSMax32x2:
|
||||
case IR::Opcode::StorageAtomicUMax32x2:
|
||||
case IR::Opcode::StorageAtomicAnd32x2:
|
||||
case IR::Opcode::StorageAtomicOr32x2:
|
||||
case IR::Opcode::StorageAtomicXor32x2:
|
||||
case IR::Opcode::StorageAtomicExchange32x2:
|
||||
info.used_storage_buffer_types |= IR::Type::U32x2;
|
||||
break;
|
||||
case IR::Opcode::LoadStorage128:
|
||||
|
|
|
|||
Loading…
Reference in a new issue