Mirrors/yuzu
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

GPU: Added Z buffer registers to Maxwell3D's reg structure.

Browse source
This commit is contained in:
Subv 2018-03-19 16:49:41 -05:00
parent 21d9519032
commit 7a27a11770
1 changed files with 17 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
src/video_core/engines/maxwell_3d.h
View file

@ -83,7 +83,22 @@ public:
}
} rt[NumRenderTargets];
INSERT_PADDING_WORDS(0x207);
INSERT_PADDING_WORDS(0x178);
struct {
u32 address_high;
u32 address_low;
u32 format;
u32 block_dimensions;
u32 layer_stride;
GPUVAddr Address() const {
return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
address_low);
}
} zeta;
INSERT_PADDING_WORDS(0x8A);
struct {
union {
@ -321,6 +336,7 @@ private:
"Field " #field_name " has invalid position")
ASSERT_REG_POSITION(rt, 0x200);
ASSERT_REG_POSITION(zeta, 0x3F8);
ASSERT_REG_POSITION(rt_control, 0x487);
ASSERT_REG_POSITION(tsc, 0x557);
ASSERT_REG_POSITION(tic, 0x55D);