Shaders: Implemented the FSET instruction.
This instruction is similar to the FSETP instruction, but it doesn't set a predicate, it sets the destination register to 1.0 if the condition holds, and 0 otherwise.
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@ -570,6 +570,59 @@ private:
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}
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}
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break;
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break;
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}
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}
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case OpCode::Type::FloatSet: {
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std::string dest = GetRegister(instr.gpr0);
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std::string op_a = instr.fset.neg_a ? "-" : "";
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op_a += GetRegister(instr.gpr8);
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if (instr.fset.abs_a) {
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op_a = "abs(" + op_a + ')';
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}
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std::string op_b = instr.fset.neg_b ? "-" : "";
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if (instr.is_b_imm) {
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std::string imm = GetImmediate19(instr);
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if (instr.fset.neg_imm)
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op_b += "(-" + imm + ')';
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else
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op_b += imm;
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} else {
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if (instr.is_b_gpr) {
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op_b += GetRegister(instr.gpr20);
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} else {
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op_b += GetUniform(instr.uniform);
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}
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}
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if (instr.fset.abs_b) {
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op_b = "abs(" + op_b + ")";
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}
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using Tegra::Shader::Pred;
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ASSERT_MSG(instr.fset.pred39 == static_cast<u64>(Pred::UnusedIndex),
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"Compound predicates are not implemented");
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// The fset instruction sets a register to 1.0 if the condition is true, and to 0
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// otherwise.
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using Tegra::Shader::PredCondition;
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switch (instr.fset.cond) {
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case PredCondition::LessThan:
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SetDest(0, dest, "((" + op_a + ") < (" + op_b + ")) ? 1.0 : 0", 1, 1);
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break;
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case PredCondition::Equal:
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SetDest(0, dest, "((" + op_a + ") == (" + op_b + ")) ? 1.0 : 0", 1, 1);
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break;
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case PredCondition::GreaterThan:
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SetDest(0, dest, "((" + op_a + ") > (" + op_b + ")) ? 1.0 : 0", 1, 1);
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break;
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default:
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NGLOG_CRITICAL(HW_GPU, "Unhandled predicate condition: {} (a: {}, b: {})",
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static_cast<unsigned>(instr.fset.cond.Value()), op_a, op_b);
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UNREACHABLE();
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}
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break;
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}
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default: {
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default: {
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switch (opcode->GetId()) {
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switch (opcode->GetId()) {
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case OpCode::Id::EXIT: {
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case OpCode::Id::EXIT: {
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