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Merge pull request #3239 from ReinUsesLisp/p2r

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shader/p2r: Implement P2R Pr
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bunnei 2019-12-31 20:37:16 -05:00 committed by GitHub
commit 028b2718ed
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GPG key ID: 4AEE18F83AFDEB23
2 changed files with 47 additions and 17 deletions
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4
src/video_core/engines/shader_bytecode.h
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@ -1051,7 +1051,7 @@ union Instruction {
BitField<40, 1, R2pMode> mode; BitField<40, 1, R2pMode> mode;
BitField<41, 2, u64> byte; BitField<41, 2, u64> byte;
BitField<20, 7, u64> immediate_mask; BitField<20, 7, u64> immediate_mask;
} r2p; } p2r_r2p;
union { union {
BitField<39, 3, u64> pred39; BitField<39, 3, u64> pred39;
@ -1801,6 +1801,7 @@ public:
PSET, PSET,
CSETP, CSETP,
R2P_IMM, R2P_IMM,
P2R_IMM,
XMAD_IMM, XMAD_IMM,
XMAD_CR, XMAD_CR,
XMAD_RC, XMAD_RC,
@ -2106,6 +2107,7 @@ private:
INST("0101000010010---", Id::PSETP, Type::PredicateSetPredicate, "PSETP"), INST("0101000010010---", Id::PSETP, Type::PredicateSetPredicate, "PSETP"),
INST("010100001010----", Id::CSETP, Type::PredicateSetPredicate, "CSETP"), INST("010100001010----", Id::CSETP, Type::PredicateSetPredicate, "CSETP"),
INST("0011100-11110---", Id::R2P_IMM, Type::RegisterSetPredicate, "R2P_IMM"), INST("0011100-11110---", Id::R2P_IMM, Type::RegisterSetPredicate, "R2P_IMM"),
INST("0011100-11101---", Id::P2R_IMM, Type::RegisterSetPredicate, "P2R_IMM"),
INST("0011011-00------", Id::XMAD_IMM, Type::Xmad, "XMAD_IMM"), INST("0011011-00------", Id::XMAD_IMM, Type::Xmad, "XMAD_IMM"),
INST("0100111---------", Id::XMAD_CR, Type::Xmad, "XMAD_CR"), INST("0100111---------", Id::XMAD_CR, Type::Xmad, "XMAD_CR"),
INST("010100010-------", Id::XMAD_RC, Type::Xmad, "XMAD_RC"), INST("010100010-------", Id::XMAD_RC, Type::Xmad, "XMAD_RC"),

46
src/video_core/shader/decode/register_set_predicate.cpp
View file

@ -13,26 +13,34 @@ namespace VideoCommon::Shader {
using Tegra::Shader::Instruction; using Tegra::Shader::Instruction;
using Tegra::Shader::OpCode; using Tegra::Shader::OpCode;
namespace {
constexpr u64 NUM_PROGRAMMABLE_PREDICATES = 7;
}
u32 ShaderIR::DecodeRegisterSetPredicate(NodeBlock& bb, u32 pc) { u32 ShaderIR::DecodeRegisterSetPredicate(NodeBlock& bb, u32 pc) {
const Instruction instr = {program_code[pc]}; const Instruction instr = {program_code[pc]};
const auto opcode = OpCode::Decode(instr); const auto opcode = OpCode::Decode(instr);
UNIMPLEMENTED_IF(instr.r2p.mode != Tegra::Shader::R2pMode::Pr); UNIMPLEMENTED_IF(instr.p2r_r2p.mode != Tegra::Shader::R2pMode::Pr);
const Node apply_mask = [&]() { const Node apply_mask = [&] {
switch (opcode->get().GetId()) { switch (opcode->get().GetId()) {
case OpCode::Id::R2P_IMM: case OpCode::Id::R2P_IMM:
return Immediate(static_cast<u32>(instr.r2p.immediate_mask)); case OpCode::Id::P2R_IMM:
return Immediate(static_cast<u32>(instr.p2r_r2p.immediate_mask));
default: default:
UNREACHABLE(); UNREACHABLE();
return Immediate(static_cast<u32>(instr.r2p.immediate_mask)); return Immediate(0);
} }
}(); }();
const Node mask = GetRegister(instr.gpr8);
const auto offset = static_cast<u32>(instr.r2p.byte) * 8;
constexpr u32 programmable_preds = 7; const auto offset = static_cast<u32>(instr.p2r_r2p.byte) * 8;
for (u64 pred = 0; pred < programmable_preds; ++pred) {
switch (opcode->get().GetId()) {
case OpCode::Id::R2P_IMM: {
const Node mask = GetRegister(instr.gpr8);
for (u64 pred = 0; pred < NUM_PROGRAMMABLE_PREDICATES; ++pred) {
const auto shift = static_cast<u32>(pred); const auto shift = static_cast<u32>(pred);
const Node apply_compare = BitfieldExtract(apply_mask, shift, 1); const Node apply_compare = BitfieldExtract(apply_mask, shift, 1);
@ -40,11 +48,31 @@ u32 ShaderIR::DecodeRegisterSetPredicate(NodeBlock& bb, u32 pc) {
Operation(OperationCode::LogicalUNotEqual, apply_compare, Immediate(0)); Operation(OperationCode::LogicalUNotEqual, apply_compare, Immediate(0));
const Node value_compare = BitfieldExtract(mask, offset + shift, 1); const Node value_compare = BitfieldExtract(mask, offset + shift, 1);
const Node value = Operation(OperationCode::LogicalUNotEqual, value_compare, Immediate(0)); const Node value =
Operation(OperationCode::LogicalUNotEqual, value_compare, Immediate(0));
const Node code = Operation(OperationCode::LogicalAssign, GetPredicate(pred), value); const Node code = Operation(OperationCode::LogicalAssign, GetPredicate(pred), value);
bb.push_back(Conditional(condition, {code})); bb.push_back(Conditional(condition, {code}));
} }
break;
}
case OpCode::Id::P2R_IMM: {
Node value = Immediate(0);
for (u64 pred = 0; pred < NUM_PROGRAMMABLE_PREDICATES; ++pred) {
Node bit = Operation(OperationCode::Select, GetPredicate(pred), Immediate(1U << pred),
Immediate(0));
value = Operation(OperationCode::UBitwiseOr, std::move(value), std::move(bit));
}
value = Operation(OperationCode::UBitwiseAnd, std::move(value), apply_mask);
value = BitfieldInsert(GetRegister(instr.gpr8), std::move(value), offset, 8);
SetRegister(bb, instr.gpr0, std::move(value));
break;
}
default:
UNIMPLEMENTED_MSG("Unhandled P2R/R2R instruction: {}", opcode->get().GetName());
break;
}
return pc; return pc;
} }