2021-05-05 06:19:08 +01:00
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include "common/common_types.h"
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#include "shader_recompiler/backend/glasm/reg_alloc.h"
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namespace Shader::IR {
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enum class Attribute : u64;
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enum class Patch : u64;
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class Inst;
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class Value;
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} // namespace Shader::IR
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namespace Shader::Backend::GLASM {
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class EmitContext;
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// Microinstruction emitters
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void EmitPhi(EmitContext& ctx, IR::Inst& inst);
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void EmitVoid(EmitContext& ctx);
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void EmitIdentity(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
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2021-05-18 06:04:22 +01:00
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void EmitConditionRef(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
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void EmitReference(EmitContext&);
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void EmitPhiMove(EmitContext& ctx, const IR::Value& phi, const IR::Value& value);
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void EmitJoin(EmitContext& ctx);
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void EmitDemoteToHelperInvocation(EmitContext& ctx);
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void EmitBarrier(EmitContext& ctx);
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void EmitWorkgroupMemoryBarrier(EmitContext& ctx);
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void EmitDeviceMemoryBarrier(EmitContext& ctx);
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void EmitPrologue(EmitContext& ctx);
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void EmitEpilogue(EmitContext& ctx);
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void EmitEmitVertex(EmitContext& ctx, const IR::Value& stream);
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void EmitEndPrimitive(EmitContext& ctx, const IR::Value& stream);
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void EmitGetRegister(EmitContext& ctx);
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void EmitSetRegister(EmitContext& ctx);
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void EmitGetPred(EmitContext& ctx);
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void EmitSetPred(EmitContext& ctx);
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void EmitSetGotoVariable(EmitContext& ctx);
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void EmitGetGotoVariable(EmitContext& ctx);
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void EmitSetIndirectBranchVariable(EmitContext& ctx);
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void EmitGetIndirectBranchVariable(EmitContext& ctx);
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void EmitGetCbufU8(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding, ScalarU32 offset);
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void EmitGetCbufS8(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding, ScalarU32 offset);
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void EmitGetCbufU16(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding, ScalarU32 offset);
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void EmitGetCbufS16(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding, ScalarU32 offset);
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void EmitGetCbufU32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding, ScalarU32 offset);
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void EmitGetCbufF32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding, ScalarU32 offset);
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void EmitGetCbufU32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding, ScalarU32 offset);
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void EmitGetAttribute(EmitContext& ctx, IR::Inst& inst, IR::Attribute attr, ScalarU32 vertex);
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void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, ScalarF32 value, ScalarU32 vertex);
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void EmitGetAttributeIndexed(EmitContext& ctx, ScalarU32 offset, ScalarU32 vertex);
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void EmitSetAttributeIndexed(EmitContext& ctx, ScalarU32 offset, ScalarF32 value, ScalarU32 vertex);
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void EmitGetPatch(EmitContext& ctx, IR::Patch patch);
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void EmitSetPatch(EmitContext& ctx, IR::Patch patch, ScalarF32 value);
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void EmitSetFragColor(EmitContext& ctx, u32 index, u32 component, ScalarF32 value);
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void EmitSetSampleMask(EmitContext& ctx, ScalarS32 value);
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void EmitSetFragDepth(EmitContext& ctx, ScalarF32 value);
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void EmitGetZFlag(EmitContext& ctx);
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void EmitGetSFlag(EmitContext& ctx);
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void EmitGetCFlag(EmitContext& ctx);
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void EmitGetOFlag(EmitContext& ctx);
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void EmitSetZFlag(EmitContext& ctx);
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void EmitSetSFlag(EmitContext& ctx);
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void EmitSetCFlag(EmitContext& ctx);
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void EmitSetOFlag(EmitContext& ctx);
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void EmitWorkgroupId(EmitContext& ctx, IR::Inst& inst);
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void EmitLocalInvocationId(EmitContext& ctx, IR::Inst& inst);
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void EmitInvocationId(EmitContext& ctx);
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void EmitSampleId(EmitContext& ctx);
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void EmitIsHelperInvocation(EmitContext& ctx);
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void EmitYDirection(EmitContext& ctx);
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void EmitLoadLocal(EmitContext& ctx, IR::Inst& inst, ScalarU32 word_offset);
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void EmitWriteLocal(EmitContext& ctx, ScalarU32 word_offset, ScalarU32 value);
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void EmitUndefU1(EmitContext& ctx);
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void EmitUndefU8(EmitContext& ctx);
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void EmitUndefU16(EmitContext& ctx);
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void EmitUndefU32(EmitContext& ctx);
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void EmitUndefU64(EmitContext& ctx);
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void EmitLoadGlobalU8(EmitContext& ctx);
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void EmitLoadGlobalS8(EmitContext& ctx);
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void EmitLoadGlobalU16(EmitContext& ctx);
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void EmitLoadGlobalS16(EmitContext& ctx);
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void EmitLoadGlobal32(EmitContext& ctx, Register address);
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void EmitLoadGlobal64(EmitContext& ctx, Register address);
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void EmitLoadGlobal128(EmitContext& ctx, Register address);
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void EmitWriteGlobalU8(EmitContext& ctx);
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void EmitWriteGlobalS8(EmitContext& ctx);
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void EmitWriteGlobalU16(EmitContext& ctx);
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void EmitWriteGlobalS16(EmitContext& ctx);
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void EmitWriteGlobal32(EmitContext& ctx, Register address, ScalarU32 value);
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void EmitWriteGlobal64(EmitContext& ctx, Register address, Register value);
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void EmitWriteGlobal128(EmitContext& ctx, Register address, Register value);
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void EmitLoadStorageU8(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset);
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void EmitLoadStorageS8(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset);
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void EmitLoadStorageU16(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset);
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void EmitLoadStorageS16(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset);
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void EmitLoadStorage32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset);
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void EmitLoadStorage64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset);
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void EmitLoadStorage128(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset);
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void EmitWriteStorageU8(EmitContext& ctx, const IR::Value& binding, ScalarU32 offset,
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ScalarU32 value);
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void EmitWriteStorageS8(EmitContext& ctx, const IR::Value& binding, ScalarU32 offset,
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ScalarS32 value);
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void EmitWriteStorageU16(EmitContext& ctx, const IR::Value& binding, ScalarU32 offset,
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ScalarU32 value);
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void EmitWriteStorageS16(EmitContext& ctx, const IR::Value& binding, ScalarU32 offset,
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ScalarS32 value);
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void EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding, ScalarU32 offset,
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ScalarU32 value);
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void EmitWriteStorage64(EmitContext& ctx, const IR::Value& binding, ScalarU32 offset,
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Register value);
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void EmitWriteStorage128(EmitContext& ctx, const IR::Value& binding, ScalarU32 offset,
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Register value);
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void EmitLoadSharedU8(EmitContext& ctx, IR::Inst& inst, ScalarU32 offset);
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void EmitLoadSharedS8(EmitContext& ctx, IR::Inst& inst, ScalarU32 offset);
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void EmitLoadSharedU16(EmitContext& ctx, IR::Inst& inst, ScalarU32 offset);
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void EmitLoadSharedS16(EmitContext& ctx, IR::Inst& inst, ScalarU32 offset);
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void EmitLoadSharedU32(EmitContext& ctx, IR::Inst& inst, ScalarU32 offset);
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void EmitLoadSharedU64(EmitContext& ctx, IR::Inst& inst, ScalarU32 offset);
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void EmitLoadSharedU128(EmitContext& ctx, IR::Inst& inst, ScalarU32 offset);
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void EmitWriteSharedU8(EmitContext& ctx, ScalarU32 offset, ScalarU32 value);
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void EmitWriteSharedU16(EmitContext& ctx, ScalarU32 offset, ScalarU32 value);
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void EmitWriteSharedU32(EmitContext& ctx, ScalarU32 offset, ScalarU32 value);
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void EmitWriteSharedU64(EmitContext& ctx, ScalarU32 offset, Register value);
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void EmitWriteSharedU128(EmitContext& ctx, ScalarU32 offset, Register value);
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void EmitCompositeConstructU32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& e1,
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const IR::Value& e2);
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void EmitCompositeConstructU32x3(EmitContext& ctx, IR::Inst& inst, const IR::Value& e1,
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const IR::Value& e2, const IR::Value& e3);
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void EmitCompositeConstructU32x4(EmitContext& ctx, IR::Inst& inst, const IR::Value& e1,
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const IR::Value& e2, const IR::Value& e3, const IR::Value& e4);
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void EmitCompositeExtractU32x2(EmitContext& ctx, IR::Inst& inst, Register composite, u32 index);
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void EmitCompositeExtractU32x3(EmitContext& ctx, IR::Inst& inst, Register composite, u32 index);
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void EmitCompositeExtractU32x4(EmitContext& ctx, IR::Inst& inst, Register composite, u32 index);
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void EmitCompositeInsertU32x2(EmitContext& ctx, Register composite, ScalarU32 object, u32 index);
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void EmitCompositeInsertU32x3(EmitContext& ctx, Register composite, ScalarU32 object, u32 index);
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void EmitCompositeInsertU32x4(EmitContext& ctx, Register composite, ScalarU32 object, u32 index);
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void EmitCompositeConstructF16x2(EmitContext& ctx, Register e1, Register e2);
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void EmitCompositeConstructF16x3(EmitContext& ctx, Register e1, Register e2, Register e3);
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void EmitCompositeConstructF16x4(EmitContext& ctx, Register e1, Register e2, Register e3,
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Register e4);
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void EmitCompositeExtractF16x2(EmitContext& ctx, Register composite, u32 index);
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void EmitCompositeExtractF16x3(EmitContext& ctx, Register composite, u32 index);
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void EmitCompositeExtractF16x4(EmitContext& ctx, Register composite, u32 index);
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void EmitCompositeInsertF16x2(EmitContext& ctx, Register composite, Register object, u32 index);
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void EmitCompositeInsertF16x3(EmitContext& ctx, Register composite, Register object, u32 index);
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void EmitCompositeInsertF16x4(EmitContext& ctx, Register composite, Register object, u32 index);
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void EmitCompositeConstructF32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& e1,
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const IR::Value& e2);
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void EmitCompositeConstructF32x3(EmitContext& ctx, IR::Inst& inst, const IR::Value& e1,
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const IR::Value& e2, const IR::Value& e3);
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void EmitCompositeConstructF32x4(EmitContext& ctx, IR::Inst& inst, const IR::Value& e1,
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const IR::Value& e2, const IR::Value& e3, const IR::Value& e4);
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void EmitCompositeExtractF32x2(EmitContext& ctx, IR::Inst& inst, Register composite, u32 index);
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void EmitCompositeExtractF32x3(EmitContext& ctx, IR::Inst& inst, Register composite, u32 index);
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void EmitCompositeExtractF32x4(EmitContext& ctx, IR::Inst& inst, Register composite, u32 index);
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void EmitCompositeInsertF32x2(EmitContext& ctx, IR::Inst& inst, Register composite,
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ScalarF32 object, u32 index);
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void EmitCompositeInsertF32x3(EmitContext& ctx, IR::Inst& inst, Register composite,
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ScalarF32 object, u32 index);
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void EmitCompositeInsertF32x4(EmitContext& ctx, IR::Inst& inst, Register composite,
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ScalarF32 object, u32 index);
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void EmitCompositeConstructF64x2(EmitContext& ctx);
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void EmitCompositeConstructF64x3(EmitContext& ctx);
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void EmitCompositeConstructF64x4(EmitContext& ctx);
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void EmitCompositeExtractF64x2(EmitContext& ctx);
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void EmitCompositeExtractF64x3(EmitContext& ctx);
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void EmitCompositeExtractF64x4(EmitContext& ctx);
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void EmitCompositeInsertF64x2(EmitContext& ctx, Register composite, Register object, u32 index);
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void EmitCompositeInsertF64x3(EmitContext& ctx, Register composite, Register object, u32 index);
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void EmitCompositeInsertF64x4(EmitContext& ctx, Register composite, Register object, u32 index);
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void EmitSelectU1(EmitContext& ctx, ScalarS32 cond, ScalarS32 true_value, ScalarS32 false_value);
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void EmitSelectU8(EmitContext& ctx, ScalarS32 cond, ScalarS32 true_value, ScalarS32 false_value);
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void EmitSelectU16(EmitContext& ctx, ScalarS32 cond, ScalarS32 true_value, ScalarS32 false_value);
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void EmitSelectU32(EmitContext& ctx, IR::Inst& inst, ScalarS32 cond, ScalarS32 true_value,
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ScalarS32 false_value);
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void EmitSelectU64(EmitContext& ctx, IR::Inst& inst, ScalarS32 cond, Register true_value,
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Register false_value);
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void EmitSelectF16(EmitContext& ctx, ScalarS32 cond, Register true_value, Register false_value);
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void EmitSelectF32(EmitContext& ctx, IR::Inst& inst, ScalarS32 cond, ScalarS32 true_value,
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ScalarS32 false_value);
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void EmitSelectF64(EmitContext& ctx, ScalarS32 cond, Register true_value, Register false_value);
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void EmitBitCastU16F16(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
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void EmitBitCastU32F32(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
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void EmitBitCastU64F64(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
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void EmitBitCastF16U16(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
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void EmitBitCastF32U32(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
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void EmitBitCastF64U64(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
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2021-05-10 02:43:29 +01:00
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void EmitPackUint2x32(EmitContext& ctx, IR::Inst& inst, Register value);
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void EmitUnpackUint2x32(EmitContext& ctx, IR::Inst& inst, Register value);
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void EmitPackFloat2x16(EmitContext& ctx, Register value);
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void EmitUnpackFloat2x16(EmitContext& ctx, Register value);
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void EmitPackHalf2x16(EmitContext& ctx, IR::Inst& inst, Register value);
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void EmitUnpackHalf2x16(EmitContext& ctx, IR::Inst& inst, Register value);
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2021-05-09 22:03:01 +01:00
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void EmitPackDouble2x32(EmitContext& ctx, IR::Inst& inst, Register value);
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void EmitUnpackDouble2x32(EmitContext& ctx, IR::Inst& inst, Register value);
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2021-05-05 06:19:08 +01:00
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void EmitGetZeroFromOp(EmitContext& ctx);
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void EmitGetSignFromOp(EmitContext& ctx);
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void EmitGetCarryFromOp(EmitContext& ctx);
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void EmitGetOverflowFromOp(EmitContext& ctx);
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void EmitGetSparseFromOp(EmitContext& ctx);
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void EmitGetInBoundsFromOp(EmitContext& ctx);
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2021-05-09 22:03:01 +01:00
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void EmitFPAbs16(EmitContext& ctx, IR::Inst& inst, Register value);
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2021-05-09 07:11:34 +01:00
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void EmitFPAbs32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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2021-05-09 22:03:01 +01:00
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void EmitFPAbs64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value);
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2021-05-09 07:11:34 +01:00
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void EmitFPAdd16(EmitContext& ctx, IR::Inst& inst, Register a, Register b);
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void EmitFPAdd32(EmitContext& ctx, IR::Inst& inst, ScalarF32 a, ScalarF32 b);
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2021-05-09 22:03:01 +01:00
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void EmitFPAdd64(EmitContext& ctx, IR::Inst& inst, ScalarF64 a, ScalarF64 b);
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2021-05-09 07:11:34 +01:00
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void EmitFPFma16(EmitContext& ctx, IR::Inst& inst, Register a, Register b, Register c);
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void EmitFPFma32(EmitContext& ctx, IR::Inst& inst, ScalarF32 a, ScalarF32 b, ScalarF32 c);
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2021-05-10 01:13:09 +01:00
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void EmitFPFma64(EmitContext& ctx, IR::Inst& inst, ScalarF64 a, ScalarF64 b, ScalarF64 c);
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2021-05-10 01:22:55 +01:00
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void EmitFPMax32(EmitContext& ctx, IR::Inst& inst, ScalarF32 a, ScalarF32 b);
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2021-05-10 01:13:09 +01:00
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void EmitFPMax64(EmitContext& ctx, IR::Inst& inst, ScalarF64 a, ScalarF64 b);
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2021-05-10 01:22:55 +01:00
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void EmitFPMin32(EmitContext& ctx, IR::Inst& inst, ScalarF32 a, ScalarF32 b);
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2021-05-10 01:13:09 +01:00
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void EmitFPMin64(EmitContext& ctx, IR::Inst& inst, ScalarF64 a, ScalarF64 b);
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2021-05-09 07:11:34 +01:00
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void EmitFPMul16(EmitContext& ctx, IR::Inst& inst, Register a, Register b);
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void EmitFPMul32(EmitContext& ctx, IR::Inst& inst, ScalarF32 a, ScalarF32 b);
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2021-05-10 01:13:09 +01:00
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void EmitFPMul64(EmitContext& ctx, IR::Inst& inst, ScalarF64 a, ScalarF64 b);
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2021-05-09 07:11:34 +01:00
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void EmitFPNeg16(EmitContext& ctx, Register value);
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void EmitFPNeg32(EmitContext& ctx, IR::Inst& inst, ScalarRegister value);
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2021-05-09 22:03:01 +01:00
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void EmitFPNeg64(EmitContext& ctx, IR::Inst& inst, Register value);
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2021-05-10 08:05:31 +01:00
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void EmitFPSin(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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void EmitFPCos(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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void EmitFPExp2(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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void EmitFPLog2(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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void EmitFPRecip32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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2021-05-09 07:11:34 +01:00
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void EmitFPRecip64(EmitContext& ctx, Register value);
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2021-05-10 08:05:31 +01:00
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void EmitFPRecipSqrt32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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2021-05-09 07:11:34 +01:00
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void EmitFPRecipSqrt64(EmitContext& ctx, Register value);
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2021-05-10 08:05:31 +01:00
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void EmitFPSqrt(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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2021-05-09 07:11:34 +01:00
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void EmitFPSaturate16(EmitContext& ctx, Register value);
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void EmitFPSaturate32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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void EmitFPSaturate64(EmitContext& ctx, Register value);
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void EmitFPClamp16(EmitContext& ctx, Register value, Register min_value, Register max_value);
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2021-05-10 02:43:29 +01:00
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void EmitFPClamp32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value, ScalarF32 min_value,
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ScalarF32 max_value);
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void EmitFPClamp64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value, ScalarF64 min_value,
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ScalarF64 max_value);
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2021-05-09 07:11:34 +01:00
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void EmitFPRoundEven16(EmitContext& ctx, Register value);
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2021-05-10 02:43:29 +01:00
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void EmitFPRoundEven32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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void EmitFPRoundEven64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value);
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2021-05-09 07:11:34 +01:00
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void EmitFPFloor16(EmitContext& ctx, Register value);
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2021-05-10 02:43:29 +01:00
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void EmitFPFloor32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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void EmitFPFloor64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value);
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2021-05-09 07:11:34 +01:00
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void EmitFPCeil16(EmitContext& ctx, Register value);
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2021-05-10 02:43:29 +01:00
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void EmitFPCeil32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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void EmitFPCeil64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value);
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2021-05-09 07:11:34 +01:00
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void EmitFPTrunc16(EmitContext& ctx, Register value);
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2021-05-10 02:43:29 +01:00
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void EmitFPTrunc32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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void EmitFPTrunc64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value);
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2021-05-09 07:11:34 +01:00
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void EmitFPOrdEqual16(EmitContext& ctx, Register lhs, Register rhs);
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void EmitFPOrdEqual32(EmitContext& ctx, IR::Inst& inst, ScalarF32 lhs, ScalarF32 rhs);
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2021-05-10 01:13:09 +01:00
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void EmitFPOrdEqual64(EmitContext& ctx, IR::Inst& inst, ScalarF64 lhs, ScalarF64 rhs);
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2021-05-09 07:11:34 +01:00
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void EmitFPUnordEqual16(EmitContext& ctx, Register lhs, Register rhs);
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2021-05-10 01:13:09 +01:00
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void EmitFPUnordEqual32(EmitContext& ctx, IR::Inst& inst, ScalarF32 lhs, ScalarF32 rhs);
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void EmitFPUnordEqual64(EmitContext& ctx, IR::Inst& inst, ScalarF64 lhs, ScalarF64 rhs);
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2021-05-09 07:11:34 +01:00
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void EmitFPOrdNotEqual16(EmitContext& ctx, Register lhs, Register rhs);
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2021-05-10 01:13:09 +01:00
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void EmitFPOrdNotEqual32(EmitContext& ctx, IR::Inst& inst, ScalarF32 lhs, ScalarF32 rhs);
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void EmitFPOrdNotEqual64(EmitContext& ctx, IR::Inst& inst, ScalarF64 lhs, ScalarF64 rhs);
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2021-05-09 07:11:34 +01:00
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void EmitFPUnordNotEqual16(EmitContext& ctx, Register lhs, Register rhs);
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2021-05-10 01:13:09 +01:00
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void EmitFPUnordNotEqual32(EmitContext& ctx, IR::Inst& inst, ScalarF32 lhs, ScalarF32 rhs);
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void EmitFPUnordNotEqual64(EmitContext& ctx, IR::Inst& inst, ScalarF64 lhs, ScalarF64 rhs);
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2021-05-09 07:11:34 +01:00
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void EmitFPOrdLessThan16(EmitContext& ctx, Register lhs, Register rhs);
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void EmitFPOrdLessThan32(EmitContext& ctx, IR::Inst& inst, ScalarF32 lhs, ScalarF32 rhs);
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2021-05-10 01:13:09 +01:00
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void EmitFPOrdLessThan64(EmitContext& ctx, IR::Inst& inst, ScalarF64 lhs, ScalarF64 rhs);
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2021-05-09 07:11:34 +01:00
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void EmitFPUnordLessThan16(EmitContext& ctx, Register lhs, Register rhs);
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2021-05-10 01:13:09 +01:00
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void EmitFPUnordLessThan32(EmitContext& ctx, IR::Inst& inst, ScalarF32 lhs, ScalarF32 rhs);
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void EmitFPUnordLessThan64(EmitContext& ctx, IR::Inst& inst, ScalarF64 lhs, ScalarF64 rhs);
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2021-05-09 07:11:34 +01:00
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void EmitFPOrdGreaterThan16(EmitContext& ctx, Register lhs, Register rhs);
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2021-05-10 01:13:09 +01:00
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void EmitFPOrdGreaterThan32(EmitContext& ctx, IR::Inst& inst, ScalarF32 lhs, ScalarF32 rhs);
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void EmitFPOrdGreaterThan64(EmitContext& ctx, IR::Inst& inst, ScalarF64 lhs, ScalarF64 rhs);
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2021-05-09 07:11:34 +01:00
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void EmitFPUnordGreaterThan16(EmitContext& ctx, Register lhs, Register rhs);
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2021-05-10 01:13:09 +01:00
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void EmitFPUnordGreaterThan32(EmitContext& ctx, IR::Inst& inst, ScalarF32 lhs, ScalarF32 rhs);
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void EmitFPUnordGreaterThan64(EmitContext& ctx, IR::Inst& inst, ScalarF64 lhs, ScalarF64 rhs);
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2021-05-09 07:11:34 +01:00
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void EmitFPOrdLessThanEqual16(EmitContext& ctx, Register lhs, Register rhs);
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void EmitFPOrdLessThanEqual32(EmitContext& ctx, IR::Inst& inst, ScalarF32 lhs, ScalarF32 rhs);
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2021-05-10 01:13:09 +01:00
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void EmitFPOrdLessThanEqual64(EmitContext& ctx, IR::Inst& inst, ScalarF64 lhs, ScalarF64 rhs);
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2021-05-09 07:11:34 +01:00
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void EmitFPUnordLessThanEqual16(EmitContext& ctx, Register lhs, Register rhs);
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2021-05-10 01:13:09 +01:00
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void EmitFPUnordLessThanEqual32(EmitContext& ctx, IR::Inst& inst, ScalarF32 lhs, ScalarF32 rhs);
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void EmitFPUnordLessThanEqual64(EmitContext& ctx, IR::Inst& inst, ScalarF64 lhs, ScalarF64 rhs);
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2021-05-09 07:11:34 +01:00
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void EmitFPOrdGreaterThanEqual16(EmitContext& ctx, Register lhs, Register rhs);
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2021-05-10 01:13:09 +01:00
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void EmitFPOrdGreaterThanEqual32(EmitContext& ctx, IR::Inst& inst, ScalarF32 lhs, ScalarF32 rhs);
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void EmitFPOrdGreaterThanEqual64(EmitContext& ctx, IR::Inst& inst, ScalarF64 lhs, ScalarF64 rhs);
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2021-05-09 07:11:34 +01:00
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void EmitFPUnordGreaterThanEqual16(EmitContext& ctx, Register lhs, Register rhs);
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2021-05-10 01:13:09 +01:00
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void EmitFPUnordGreaterThanEqual32(EmitContext& ctx, IR::Inst& inst, ScalarF32 lhs, ScalarF32 rhs);
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void EmitFPUnordGreaterThanEqual64(EmitContext& ctx, IR::Inst& inst, ScalarF64 lhs, ScalarF64 rhs);
|
2021-05-09 07:11:34 +01:00
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|
void EmitFPIsNan16(EmitContext& ctx, Register value);
|
2021-05-10 01:13:09 +01:00
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void EmitFPIsNan32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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void EmitFPIsNan64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value);
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2021-05-09 07:11:34 +01:00
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void EmitIAdd32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
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void EmitIAdd64(EmitContext& ctx, Register a, Register b);
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void EmitISub32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
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void EmitISub64(EmitContext& ctx, Register a, Register b);
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void EmitIMul32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
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2021-05-09 23:49:27 +01:00
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void EmitINeg32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
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2021-05-10 07:55:33 +01:00
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void EmitINeg64(EmitContext& ctx, IR::Inst& inst, Register value);
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2021-05-09 23:49:27 +01:00
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void EmitIAbs32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
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2021-05-10 07:55:33 +01:00
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void EmitIAbs64(EmitContext& ctx, IR::Inst& inst, Register value);
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2021-05-09 07:11:34 +01:00
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void EmitShiftLeftLogical32(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 shift);
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void EmitShiftLeftLogical64(EmitContext& ctx, Register base, Register shift);
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2021-05-09 23:49:27 +01:00
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void EmitShiftRightLogical32(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 shift);
|
2021-05-09 07:11:34 +01:00
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void EmitShiftRightLogical64(EmitContext& ctx, Register base, Register shift);
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2021-05-09 23:49:27 +01:00
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void EmitShiftRightArithmetic32(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 shift);
|
2021-05-09 07:11:34 +01:00
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void EmitShiftRightArithmetic64(EmitContext& ctx, Register base, Register shift);
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void EmitBitwiseAnd32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
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void EmitBitwiseOr32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
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void EmitBitwiseXor32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
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2021-05-09 22:57:57 +01:00
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void EmitBitFieldInsert(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 insert,
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ScalarS32 offset, ScalarS32 count);
|
2021-05-09 07:11:34 +01:00
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void EmitBitFieldSExtract(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 offset,
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ScalarS32 count);
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void EmitBitFieldUExtract(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 offset,
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ScalarU32 count);
|
2021-05-09 22:57:57 +01:00
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void EmitBitReverse32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
|
2021-05-09 23:49:27 +01:00
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void EmitBitCount32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
|
2021-05-09 22:57:57 +01:00
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void EmitBitwiseNot32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
|
2021-05-09 23:49:27 +01:00
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void EmitFindSMsb32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
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void EmitFindUMsb32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value);
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void EmitSMin32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
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void EmitUMin32(EmitContext& ctx, IR::Inst& inst, ScalarU32 a, ScalarU32 b);
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void EmitSMax32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
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void EmitUMax32(EmitContext& ctx, IR::Inst& inst, ScalarU32 a, ScalarU32 b);
|
2021-05-09 07:11:34 +01:00
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void EmitSClamp32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value, ScalarS32 min, ScalarS32 max);
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void EmitUClamp32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 min, ScalarU32 max);
|
2021-05-09 22:57:57 +01:00
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|
void EmitSLessThan(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs);
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void EmitULessThan(EmitContext& ctx, IR::Inst& inst, ScalarU32 lhs, ScalarU32 rhs);
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void EmitIEqual(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs);
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void EmitSLessThanEqual(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs);
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void EmitULessThanEqual(EmitContext& ctx, IR::Inst& inst, ScalarU32 lhs, ScalarU32 rhs);
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void EmitSGreaterThan(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs);
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void EmitUGreaterThan(EmitContext& ctx, IR::Inst& inst, ScalarU32 lhs, ScalarU32 rhs);
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void EmitINotEqual(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs);
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void EmitSGreaterThanEqual(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs);
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void EmitUGreaterThanEqual(EmitContext& ctx, IR::Inst& inst, ScalarU32 lhs, ScalarU32 rhs);
|
2021-05-11 03:35:16 +01:00
|
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|
void EmitSharedAtomicIAdd32(EmitContext& ctx, IR::Inst& inst, ScalarU32 pointer_offset,
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|
ScalarU32 value);
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void EmitSharedAtomicSMin32(EmitContext& ctx, IR::Inst& inst, ScalarU32 pointer_offset,
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|
ScalarS32 value);
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void EmitSharedAtomicUMin32(EmitContext& ctx, IR::Inst& inst, ScalarU32 pointer_offset,
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|
ScalarU32 value);
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void EmitSharedAtomicSMax32(EmitContext& ctx, IR::Inst& inst, ScalarU32 pointer_offset,
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|
ScalarS32 value);
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void EmitSharedAtomicUMax32(EmitContext& ctx, IR::Inst& inst, ScalarU32 pointer_offset,
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ScalarU32 value);
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void EmitSharedAtomicInc32(EmitContext& ctx, IR::Inst& inst, ScalarU32 pointer_offset,
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ScalarU32 value);
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void EmitSharedAtomicDec32(EmitContext& ctx, IR::Inst& inst, ScalarU32 pointer_offset,
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|
ScalarU32 value);
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void EmitSharedAtomicAnd32(EmitContext& ctx, IR::Inst& inst, ScalarU32 pointer_offset,
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|
ScalarU32 value);
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void EmitSharedAtomicOr32(EmitContext& ctx, IR::Inst& inst, ScalarU32 pointer_offset,
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|
ScalarU32 value);
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void EmitSharedAtomicXor32(EmitContext& ctx, IR::Inst& inst, ScalarU32 pointer_offset,
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|
ScalarU32 value);
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void EmitSharedAtomicExchange32(EmitContext& ctx, IR::Inst& inst, ScalarU32 pointer_offset,
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|
ScalarU32 value);
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void EmitSharedAtomicExchange64(EmitContext& ctx, IR::Inst& inst, ScalarU32 pointer_offset,
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|
Register value);
|
2021-05-10 03:01:03 +01:00
|
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|
void EmitStorageAtomicIAdd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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|
ScalarU32 offset, ScalarU32 value);
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void EmitStorageAtomicSMin32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, ScalarS32 value);
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void EmitStorageAtomicUMin32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, ScalarU32 value);
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void EmitStorageAtomicSMax32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, ScalarS32 value);
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void EmitStorageAtomicUMax32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, ScalarU32 value);
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void EmitStorageAtomicInc32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, ScalarU32 value);
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void EmitStorageAtomicDec32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, ScalarU32 value);
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void EmitStorageAtomicAnd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, ScalarU32 value);
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void EmitStorageAtomicOr32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, ScalarU32 value);
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void EmitStorageAtomicXor32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, ScalarU32 value);
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void EmitStorageAtomicExchange32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, ScalarU32 value);
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void EmitStorageAtomicIAdd64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicSMin64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicUMin64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicSMax64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicUMax64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicAnd64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicOr64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicXor64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicExchange64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicAddF32(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, ScalarF32 value);
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void EmitStorageAtomicAddF16x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicAddF32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicMinF16x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicMinF32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicMaxF16x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
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void EmitStorageAtomicMaxF32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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ScalarU32 offset, Register value);
|
2021-05-05 06:19:08 +01:00
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void EmitGlobalAtomicIAdd32(EmitContext& ctx);
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void EmitGlobalAtomicSMin32(EmitContext& ctx);
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void EmitGlobalAtomicUMin32(EmitContext& ctx);
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void EmitGlobalAtomicSMax32(EmitContext& ctx);
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void EmitGlobalAtomicUMax32(EmitContext& ctx);
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void EmitGlobalAtomicInc32(EmitContext& ctx);
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void EmitGlobalAtomicDec32(EmitContext& ctx);
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void EmitGlobalAtomicAnd32(EmitContext& ctx);
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void EmitGlobalAtomicOr32(EmitContext& ctx);
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void EmitGlobalAtomicXor32(EmitContext& ctx);
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void EmitGlobalAtomicExchange32(EmitContext& ctx);
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void EmitGlobalAtomicIAdd64(EmitContext& ctx);
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void EmitGlobalAtomicSMin64(EmitContext& ctx);
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void EmitGlobalAtomicUMin64(EmitContext& ctx);
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void EmitGlobalAtomicSMax64(EmitContext& ctx);
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void EmitGlobalAtomicUMax64(EmitContext& ctx);
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void EmitGlobalAtomicInc64(EmitContext& ctx);
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void EmitGlobalAtomicDec64(EmitContext& ctx);
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void EmitGlobalAtomicAnd64(EmitContext& ctx);
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void EmitGlobalAtomicOr64(EmitContext& ctx);
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void EmitGlobalAtomicXor64(EmitContext& ctx);
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void EmitGlobalAtomicExchange64(EmitContext& ctx);
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void EmitGlobalAtomicAddF32(EmitContext& ctx);
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void EmitGlobalAtomicAddF16x2(EmitContext& ctx);
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void EmitGlobalAtomicAddF32x2(EmitContext& ctx);
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void EmitGlobalAtomicMinF16x2(EmitContext& ctx);
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void EmitGlobalAtomicMinF32x2(EmitContext& ctx);
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void EmitGlobalAtomicMaxF16x2(EmitContext& ctx);
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void EmitGlobalAtomicMaxF32x2(EmitContext& ctx);
|
2021-05-10 01:17:48 +01:00
|
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|
void EmitLogicalOr(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
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void EmitLogicalAnd(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
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void EmitLogicalXor(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
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void EmitLogicalNot(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
|
2021-05-10 02:43:29 +01:00
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|
void EmitConvertS16F16(EmitContext& ctx, IR::Inst& inst, Register value);
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void EmitConvertS16F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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void EmitConvertS16F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value);
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void EmitConvertS32F16(EmitContext& ctx, IR::Inst& inst, Register value);
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void EmitConvertS32F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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void EmitConvertS32F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value);
|
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|
void EmitConvertS64F16(EmitContext& ctx, IR::Inst& inst, Register value);
|
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void EmitConvertS64F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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void EmitConvertS64F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value);
|
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|
void EmitConvertU16F16(EmitContext& ctx, IR::Inst& inst, Register value);
|
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void EmitConvertU16F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
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void EmitConvertU16F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value);
|
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|
void EmitConvertU32F16(EmitContext& ctx, IR::Inst& inst, Register value);
|
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|
void EmitConvertU32F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
|
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|
void EmitConvertU32F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value);
|
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|
void EmitConvertU64F16(EmitContext& ctx, IR::Inst& inst, Register value);
|
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|
void EmitConvertU64F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
|
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|
void EmitConvertU64F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value);
|
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|
void EmitConvertU64U32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value);
|
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|
void EmitConvertU32U64(EmitContext& ctx, IR::Inst& inst, Register value);
|
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|
void EmitConvertF16F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
|
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|
void EmitConvertF32F16(EmitContext& ctx, IR::Inst& inst, Register value);
|
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|
void EmitConvertF32F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value);
|
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|
void EmitConvertF64F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value);
|
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|
|
void EmitConvertF16S8(EmitContext& ctx, IR::Inst& inst, Register value);
|
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|
void EmitConvertF16S16(EmitContext& ctx, IR::Inst& inst, Register value);
|
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|
void EmitConvertF16S32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
|
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|
|
void EmitConvertF16S64(EmitContext& ctx, IR::Inst& inst, Register value);
|
|
|
|
|
void EmitConvertF16U8(EmitContext& ctx, IR::Inst& inst, Register value);
|
|
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|
|
void EmitConvertF16U16(EmitContext& ctx, IR::Inst& inst, Register value);
|
|
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|
|
void EmitConvertF16U32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value);
|
|
|
|
|
void EmitConvertF16U64(EmitContext& ctx, IR::Inst& inst, Register value);
|
|
|
|
|
void EmitConvertF32S8(EmitContext& ctx, IR::Inst& inst, Register value);
|
|
|
|
|
void EmitConvertF32S16(EmitContext& ctx, IR::Inst& inst, Register value);
|
|
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|
|
void EmitConvertF32S32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
|
|
|
|
|
void EmitConvertF32S64(EmitContext& ctx, IR::Inst& inst, Register value);
|
|
|
|
|
void EmitConvertF32U8(EmitContext& ctx, IR::Inst& inst, Register value);
|
|
|
|
|
void EmitConvertF32U16(EmitContext& ctx, IR::Inst& inst, Register value);
|
|
|
|
|
void EmitConvertF32U32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value);
|
|
|
|
|
void EmitConvertF32U64(EmitContext& ctx, IR::Inst& inst, Register value);
|
|
|
|
|
void EmitConvertF64S8(EmitContext& ctx, IR::Inst& inst, Register value);
|
|
|
|
|
void EmitConvertF64S16(EmitContext& ctx, IR::Inst& inst, Register value);
|
|
|
|
|
void EmitConvertF64S32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
|
|
|
|
|
void EmitConvertF64S64(EmitContext& ctx, IR::Inst& inst, Register value);
|
|
|
|
|
void EmitConvertF64U8(EmitContext& ctx, IR::Inst& inst, Register value);
|
|
|
|
|
void EmitConvertF64U16(EmitContext& ctx, IR::Inst& inst, Register value);
|
|
|
|
|
void EmitConvertF64U32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value);
|
|
|
|
|
void EmitConvertF64U64(EmitContext& ctx, IR::Inst& inst, Register value);
|
2021-05-05 06:19:08 +01:00
|
|
|
void EmitBindlessImageSampleImplicitLod(EmitContext&);
|
|
|
|
|
void EmitBindlessImageSampleExplicitLod(EmitContext&);
|
|
|
|
|
void EmitBindlessImageSampleDrefImplicitLod(EmitContext&);
|
|
|
|
|
void EmitBindlessImageSampleDrefExplicitLod(EmitContext&);
|
|
|
|
|
void EmitBindlessImageGather(EmitContext&);
|
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|
|
|
void EmitBindlessImageGatherDref(EmitContext&);
|
|
|
|
|
void EmitBindlessImageFetch(EmitContext&);
|
|
|
|
|
void EmitBindlessImageQueryDimensions(EmitContext&);
|
|
|
|
|
void EmitBindlessImageQueryLod(EmitContext&);
|
|
|
|
|
void EmitBindlessImageGradient(EmitContext&);
|
|
|
|
|
void EmitBindlessImageRead(EmitContext&);
|
|
|
|
|
void EmitBindlessImageWrite(EmitContext&);
|
|
|
|
|
void EmitBoundImageSampleImplicitLod(EmitContext&);
|
|
|
|
|
void EmitBoundImageSampleExplicitLod(EmitContext&);
|
|
|
|
|
void EmitBoundImageSampleDrefImplicitLod(EmitContext&);
|
|
|
|
|
void EmitBoundImageSampleDrefExplicitLod(EmitContext&);
|
|
|
|
|
void EmitBoundImageGather(EmitContext&);
|
|
|
|
|
void EmitBoundImageGatherDref(EmitContext&);
|
|
|
|
|
void EmitBoundImageFetch(EmitContext&);
|
|
|
|
|
void EmitBoundImageQueryDimensions(EmitContext&);
|
|
|
|
|
void EmitBoundImageQueryLod(EmitContext&);
|
|
|
|
|
void EmitBoundImageGradient(EmitContext&);
|
|
|
|
|
void EmitBoundImageRead(EmitContext&);
|
|
|
|
|
void EmitBoundImageWrite(EmitContext&);
|
2021-05-08 20:28:52 +01:00
|
|
|
void EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-16 21:54:43 +01:00
|
|
|
const IR::Value& coord, Register bias_lc, const IR::Value& offset);
|
2021-05-08 20:28:52 +01:00
|
|
|
void EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-17 06:52:01 +01:00
|
|
|
const IR::Value& coord, ScalarF32 lod, const IR::Value& offset);
|
2021-05-08 20:28:52 +01:00
|
|
|
void EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-17 06:52:01 +01:00
|
|
|
const IR::Value& coord, ScalarF32 dref, Register bias_lc,
|
2021-05-09 07:11:34 +01:00
|
|
|
const IR::Value& offset);
|
2021-05-08 20:28:52 +01:00
|
|
|
void EmitImageSampleDrefExplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-17 06:52:01 +01:00
|
|
|
const IR::Value& coord, ScalarF32 dref, ScalarF32 lod,
|
2021-05-09 07:11:34 +01:00
|
|
|
const IR::Value& offset);
|
2021-05-18 23:43:52 +01:00
|
|
|
void EmitImageGather(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
|
|
|
|
const IR::Value& coord, const IR::Value& offset, const IR::Value& offset2);
|
|
|
|
|
void EmitImageGatherDref(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
|
|
|
|
const IR::Value& coord, const IR::Value& offset, const IR::Value& offset2,
|
|
|
|
|
const IR::Value& dref);
|
2021-05-16 21:54:43 +01:00
|
|
|
void EmitImageFetch(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
2021-05-09 07:11:34 +01:00
|
|
|
Register offset, Register lod, Register ms);
|
2021-05-08 20:28:52 +01:00
|
|
|
void EmitImageQueryDimensions(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-19 01:05:46 +01:00
|
|
|
ScalarF32 lod);
|
2021-05-16 21:54:43 +01:00
|
|
|
void EmitImageQueryLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord);
|
|
|
|
|
void EmitImageGradient(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
2021-05-09 07:11:34 +01:00
|
|
|
Register derivates, Register offset, Register lod_clamp);
|
2021-05-16 21:54:43 +01:00
|
|
|
void EmitImageRead(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord);
|
|
|
|
|
void EmitImageWrite(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
2021-05-09 07:11:34 +01:00
|
|
|
Register color);
|
2021-05-05 06:19:08 +01:00
|
|
|
void EmitBindlessImageAtomicIAdd32(EmitContext&);
|
|
|
|
|
void EmitBindlessImageAtomicSMin32(EmitContext&);
|
|
|
|
|
void EmitBindlessImageAtomicUMin32(EmitContext&);
|
|
|
|
|
void EmitBindlessImageAtomicSMax32(EmitContext&);
|
|
|
|
|
void EmitBindlessImageAtomicUMax32(EmitContext&);
|
|
|
|
|
void EmitBindlessImageAtomicInc32(EmitContext&);
|
|
|
|
|
void EmitBindlessImageAtomicDec32(EmitContext&);
|
|
|
|
|
void EmitBindlessImageAtomicAnd32(EmitContext&);
|
|
|
|
|
void EmitBindlessImageAtomicOr32(EmitContext&);
|
|
|
|
|
void EmitBindlessImageAtomicXor32(EmitContext&);
|
|
|
|
|
void EmitBindlessImageAtomicExchange32(EmitContext&);
|
|
|
|
|
void EmitBoundImageAtomicIAdd32(EmitContext&);
|
|
|
|
|
void EmitBoundImageAtomicSMin32(EmitContext&);
|
|
|
|
|
void EmitBoundImageAtomicUMin32(EmitContext&);
|
|
|
|
|
void EmitBoundImageAtomicSMax32(EmitContext&);
|
|
|
|
|
void EmitBoundImageAtomicUMax32(EmitContext&);
|
|
|
|
|
void EmitBoundImageAtomicInc32(EmitContext&);
|
|
|
|
|
void EmitBoundImageAtomicDec32(EmitContext&);
|
|
|
|
|
void EmitBoundImageAtomicAnd32(EmitContext&);
|
|
|
|
|
void EmitBoundImageAtomicOr32(EmitContext&);
|
|
|
|
|
void EmitBoundImageAtomicXor32(EmitContext&);
|
|
|
|
|
void EmitBoundImageAtomicExchange32(EmitContext&);
|
2021-05-16 21:54:43 +01:00
|
|
|
void EmitImageAtomicIAdd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
|
|
|
ScalarU32 value);
|
|
|
|
|
void EmitImageAtomicSMin32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
|
|
|
ScalarS32 value);
|
|
|
|
|
void EmitImageAtomicUMin32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
|
|
|
ScalarU32 value);
|
|
|
|
|
void EmitImageAtomicSMax32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
|
|
|
ScalarS32 value);
|
|
|
|
|
void EmitImageAtomicUMax32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
|
|
|
ScalarU32 value);
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void EmitImageAtomicInc32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
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2021-05-09 07:11:34 +01:00
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ScalarU32 value);
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2021-05-16 21:54:43 +01:00
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void EmitImageAtomicDec32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
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2021-05-09 07:11:34 +01:00
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ScalarU32 value);
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2021-05-16 21:54:43 +01:00
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void EmitImageAtomicAnd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
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2021-05-09 07:11:34 +01:00
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ScalarU32 value);
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2021-05-16 21:54:43 +01:00
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void EmitImageAtomicOr32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
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2021-05-09 07:11:34 +01:00
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ScalarU32 value);
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2021-05-16 21:54:43 +01:00
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void EmitImageAtomicXor32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
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2021-05-09 07:11:34 +01:00
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ScalarU32 value);
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2021-05-08 20:28:52 +01:00
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void EmitImageAtomicExchange32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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2021-05-16 21:54:43 +01:00
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Register coord, ScalarU32 value);
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2021-05-10 22:21:28 +01:00
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void EmitLaneId(EmitContext& ctx, IR::Inst& inst);
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void EmitVoteAll(EmitContext& ctx, IR::Inst& inst, ScalarS32 pred);
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void EmitVoteAny(EmitContext& ctx, IR::Inst& inst, ScalarS32 pred);
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void EmitVoteEqual(EmitContext& ctx, IR::Inst& inst, ScalarS32 pred);
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void EmitSubgroupBallot(EmitContext& ctx, IR::Inst& inst, ScalarS32 pred);
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void EmitSubgroupEqMask(EmitContext& ctx, IR::Inst& inst);
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void EmitSubgroupLtMask(EmitContext& ctx, IR::Inst& inst);
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void EmitSubgroupLeMask(EmitContext& ctx, IR::Inst& inst);
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void EmitSubgroupGtMask(EmitContext& ctx, IR::Inst& inst);
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void EmitSubgroupGeMask(EmitContext& ctx, IR::Inst& inst);
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2021-05-09 07:11:34 +01:00
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void EmitShuffleIndex(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 index,
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2021-05-10 22:21:28 +01:00
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const IR::Value& clamp, const IR::Value& segmentation_mask);
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2021-05-09 07:11:34 +01:00
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void EmitShuffleUp(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 index,
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2021-05-10 22:21:28 +01:00
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const IR::Value& clamp, const IR::Value& segmentation_mask);
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2021-05-09 07:11:34 +01:00
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void EmitShuffleDown(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 index,
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2021-05-10 22:21:28 +01:00
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const IR::Value& clamp, const IR::Value& segmentation_mask);
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2021-05-09 07:11:34 +01:00
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void EmitShuffleButterfly(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 index,
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2021-05-10 22:21:28 +01:00
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const IR::Value& clamp, const IR::Value& segmentation_mask);
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2021-05-09 07:11:34 +01:00
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void EmitFSwizzleAdd(EmitContext& ctx, ScalarF32 op_a, ScalarF32 op_b, ScalarU32 swizzle);
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2021-05-15 22:17:03 +01:00
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void EmitDPdxFine(EmitContext& ctx, IR::Inst& inst, ScalarF32 op_a);
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void EmitDPdyFine(EmitContext& ctx, IR::Inst& inst, ScalarF32 op_a);
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void EmitDPdxCoarse(EmitContext& ctx, IR::Inst& inst, ScalarF32 op_a);
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void EmitDPdyCoarse(EmitContext& ctx, IR::Inst& inst, ScalarF32 op_a);
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2021-05-05 06:19:08 +01:00
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} // namespace Shader::Backend::GLASM
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