2015-07-22 00:38:59 +01:00
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// Copyright 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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2015-07-23 04:25:30 +01:00
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#include <memory>
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#include <unordered_map>
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#include "common/hash.h"
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#include "common/make_unique.h"
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2015-07-22 00:38:59 +01:00
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#include "common/profiler.h"
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#include "video_core/debug_utils/debug_utils.h"
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#include "video_core/pica.h"
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2015-07-23 04:25:30 +01:00
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#include "video_core/video_core.h"
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2015-07-22 00:38:59 +01:00
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#include "shader.h"
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#include "shader_interpreter.h"
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2015-08-12 05:00:44 +01:00
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2015-08-15 03:29:08 +01:00
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#ifdef ARCHITECTURE_x86_64
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2015-08-12 05:00:44 +01:00
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#include "shader_jit_x64.h"
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2015-08-15 03:29:08 +01:00
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#endif // ARCHITECTURE_x86_64
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2015-07-22 00:38:59 +01:00
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namespace Pica {
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namespace Shader {
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2015-07-23 04:25:30 +01:00
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#ifdef ARCHITECTURE_x86_64
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static std::unordered_map<u64, CompiledShader*> shader_map;
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static JitCompiler jit;
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static CompiledShader* jit_shader;
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#endif // ARCHITECTURE_x86_64
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2015-07-22 00:38:59 +01:00
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void Setup(UnitState& state) {
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2015-07-23 04:25:30 +01:00
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#ifdef ARCHITECTURE_x86_64
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if (VideoCore::g_shader_jit_enabled) {
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u64 cache_key = (Common::ComputeHash64(&g_state.vs.program_code, sizeof(g_state.vs.program_code)) ^
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Common::ComputeHash64(&g_state.vs.swizzle_data, sizeof(g_state.vs.swizzle_data)) ^
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g_state.regs.vs.main_offset);
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auto iter = shader_map.find(cache_key);
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if (iter != shader_map.end()) {
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jit_shader = iter->second;
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} else {
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jit_shader = jit.Compile();
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shader_map.emplace(cache_key, jit_shader);
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}
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2015-08-15 03:29:08 +01:00
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}
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#endif // ARCHITECTURE_x86_64
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2015-07-23 04:25:30 +01:00
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}
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void Shutdown() {
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shader_map.clear();
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2015-07-22 00:38:59 +01:00
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}
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static Common::Profiling::TimingCategory shader_category("Vertex Shader");
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OutputVertex Run(UnitState& state, const InputVertex& input, int num_attributes) {
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auto& config = g_state.regs.vs;
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auto& setup = g_state.vs;
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Common::Profiling::ScopeTimer timer(shader_category);
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state.program_counter = config.main_offset;
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state.debug.max_offset = 0;
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state.debug.max_opdesc_id = 0;
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// Setup input register table
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const auto& attribute_register_map = config.input_register_map;
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2015-08-15 21:51:32 +01:00
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if (num_attributes > 0) state.registers.input[attribute_register_map.attribute0_register] = input.attr[0];
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if (num_attributes > 1) state.registers.input[attribute_register_map.attribute1_register] = input.attr[1];
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if (num_attributes > 2) state.registers.input[attribute_register_map.attribute2_register] = input.attr[2];
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if (num_attributes > 3) state.registers.input[attribute_register_map.attribute3_register] = input.attr[3];
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if (num_attributes > 4) state.registers.input[attribute_register_map.attribute4_register] = input.attr[4];
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if (num_attributes > 5) state.registers.input[attribute_register_map.attribute5_register] = input.attr[5];
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if (num_attributes > 6) state.registers.input[attribute_register_map.attribute6_register] = input.attr[6];
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if (num_attributes > 7) state.registers.input[attribute_register_map.attribute7_register] = input.attr[7];
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if (num_attributes > 8) state.registers.input[attribute_register_map.attribute8_register] = input.attr[8];
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if (num_attributes > 9) state.registers.input[attribute_register_map.attribute9_register] = input.attr[9];
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if (num_attributes > 10) state.registers.input[attribute_register_map.attribute10_register] = input.attr[10];
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if (num_attributes > 11) state.registers.input[attribute_register_map.attribute11_register] = input.attr[11];
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if (num_attributes > 12) state.registers.input[attribute_register_map.attribute12_register] = input.attr[12];
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if (num_attributes > 13) state.registers.input[attribute_register_map.attribute13_register] = input.attr[13];
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if (num_attributes > 14) state.registers.input[attribute_register_map.attribute14_register] = input.attr[14];
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if (num_attributes > 15) state.registers.input[attribute_register_map.attribute15_register] = input.attr[15];
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2015-07-22 00:38:59 +01:00
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state.conditional_code[0] = false;
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state.conditional_code[1] = false;
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2015-07-23 04:25:30 +01:00
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#ifdef ARCHITECTURE_x86_64
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if (VideoCore::g_shader_jit_enabled)
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2015-08-15 21:51:32 +01:00
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jit_shader(&state.registers);
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2015-07-23 04:25:30 +01:00
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else
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RunInterpreter(state);
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#else
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2015-07-22 00:38:59 +01:00
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RunInterpreter(state);
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2015-08-15 03:29:08 +01:00
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#endif // ARCHITECTURE_x86_64
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2015-07-22 00:38:59 +01:00
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// Setup output data
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OutputVertex ret;
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// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
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// figure out what those circumstances are and enable the remaining outputs then.
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for (int i = 0; i < 7; ++i) {
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const auto& output_register_map = g_state.regs.vs_output_attributes[i]; // TODO: Don't hardcode VS here
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u32 semantics[4] = {
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output_register_map.map_x, output_register_map.map_y,
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output_register_map.map_z, output_register_map.map_w
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};
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for (int comp = 0; comp < 4; ++comp) {
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float24* out = ((float24*)&ret) + semantics[comp];
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if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
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2015-08-15 21:51:32 +01:00
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*out = state.registers.output[i][comp];
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2015-07-22 00:38:59 +01:00
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} else {
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// Zero output so that attributes which aren't output won't have denormals in them,
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// which would slow us down later.
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memset(out, 0, sizeof(*out));
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}
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}
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}
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// The hardware takes the absolute and saturates vertex colors like this, *before* doing interpolation
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for (int i = 0; i < 4; ++i) {
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ret.color[i] = float24::FromFloat32(
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std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
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}
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LOG_TRACE(Render_Software, "Output vertex: pos (%.2f, %.2f, %.2f, %.2f), col(%.2f, %.2f, %.2f, %.2f), tc0(%.2f, %.2f)",
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ret.pos.x.ToFloat32(), ret.pos.y.ToFloat32(), ret.pos.z.ToFloat32(), ret.pos.w.ToFloat32(),
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ret.color.x.ToFloat32(), ret.color.y.ToFloat32(), ret.color.z.ToFloat32(), ret.color.w.ToFloat32(),
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ret.tc0.u().ToFloat32(), ret.tc0.v().ToFloat32());
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return ret;
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}
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} // namespace Shader
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} // namespace Pica
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