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Author SHA1 Message Date
N00byKing
5ded39f5d8
CITRA_ICON -> YUZU_ICON 2018-03-23 16:56:59 +01:00
bunnei
633abd5a94
Merge pull request #264 from valentinvanelslande/cmd-dynarmic 
yuzu_cmd: change default cpu core to dynarmic
 2018-03-22 23:53:15 -04:00
Valentin Vanelslande
ee5f5a2c2d
yuzu_cmd: change default cpu core to dynarmic 2018-03-22 19:44:34 -06:00
Valentin Vanelslande
47cac816f6
default_ini: change default cpu core to dynarmic 2018-03-22 19:43:59 -06:00
bunnei
4daf91fc69
Merge pull request #263 from N00byKing/non3ds 
Remove more N3DS References
 2018-03-22 18:02:51 -04:00
N00byKing
8afdbf6a1f Remove more N3DS References 2018-03-22 21:25:06 +01:00
bunnei
b5c03088bc
Merge pull request #261 from mailwl/spl 
Service/spl: add module and services
 2018-03-22 10:28:28 -04:00
mailwl
95e747cd06 Service/spl: add module and services 2018-03-22 09:55:14 +03:00
bunnei
ec5ede68e7
Merge pull request #258 from Subv/gpu_attribs 
GPU: Added vertex attrib format and triangle topology registers
 2018-03-21 19:36:06 -04:00
bunnei
2ab021da14
Merge pull request #260 from N00byKing/3535 
Implement Pull #3535 from citra: CMake: Set EMU_ARCH_BITS in CMakeLists.txt
 2018-03-21 18:49:00 -04:00
bunnei
7fa3bf02ca
Merge pull request #259 from N00byKing/usehttps 
Use HTTPS for lz4
 2018-03-21 18:48:39 -04:00
N00byKing
34b733e70e CMake: Set EMU_ARCH_BITS in CMakeLists.txt 2018-03-21 19:03:20 +01:00
N00byKing
3cdf6c536d Use HTTPS for Submodule lz4 2018-03-21 19:01:54 +01:00
bunnei
4721ea4523
Merge pull request #257 from mailwl/vi-module 
Service/vi: convert services to module
 2018-03-21 10:48:15 -04:00
Subv
c450d264eb GPU: Added vertex attribute format registers. 2018-03-21 09:26:47 -05:00
mailwl
6673ed1274 Service/vi: convert services to module 2018-03-21 13:09:40 +03:00
Subv
ae28a52277 GPU: Added registers for the number of vertices to render. 2018-03-20 23:28:06 -05:00
bunnei
0b3ab30762
Merge pull request #254 from bunnei/port-citra-renderer 
Port Citra OpenGL rasterizer code
 2018-03-20 21:37:43 -04:00
bunnei
8c8de2efe9
Merge pull request #256 from mailwl/fatal 
Service: add fatal:u, fatal:p services
 2018-03-20 11:12:39 -04:00
mailwl
dca7cfb9cf Service: add fatal:u, fatal:p services 2018-03-20 16:59:02 +03:00
bunnei
6e3222363c renderer_gl: Port boilerplate rasterizer code over from Citra. 2018-03-20 00:07:32 -04:00
bunnei
9c468e0c55 gl_shader_util: Sync latest version with Citra. 2018-03-20 00:07:31 -04:00
bunnei
d7b1ebe4a8 renderer_gl: Port over gl_shader_gen module from Citra. 2018-03-20 00:07:30 -04:00
Mat M
f4700ccabf
Merge pull request #253 from Subv/rt_depth 
GPU: Added registers for color and Z buffers.
 2018-03-19 23:37:47 -04:00
bunnei
4bdb46e4c2 renderer_gl: Port over gl_shader_decompiler module from Citra. 2018-03-19 23:14:03 -04:00
bunnei
a3e10b1a72 renderer_gl: Port over gl_rasterizer_cache module from Citra. 2018-03-19 23:14:03 -04:00
bunnei
db0cfb8e8b gl_resource_manager: Sync latest version with Citra. 2018-03-19 23:14:02 -04:00
bunnei
0e4b9cdde4 renderer_gl: Port over gl_stream_buffer module from Citra. 2018-03-19 23:14:02 -04:00
bunnei
a1cf5020e6 externals: Update Glad to latest version used by Citra. 2018-03-19 23:14:01 -04:00
bunnei
6a0902e56d gl_state: Sync latest version with Citra. 2018-03-19 23:13:49 -04:00
Subv
7a27a11770 GPU: Added Z buffer registers to Maxwell3D's reg structure. 2018-03-19 16:55:33 -05:00
Subv
21d9519032 GPU: Added the render target (RT) registers to Maxwell3D's reg structure. 2018-03-19 16:46:29 -05:00
bunnei
a90ab1dec7
Merge pull request #252 from N00byKing/3064 
Implement Pull #3064 from citra: Clean all format warnings (Yuzu-specific format warnings cleared too)
 2018-03-19 16:29:03 -04:00
N00byKing
1d8b6ad13b Clang Fixes 2018-03-19 17:53:35 +01:00
N00byKing
d16e08454d
oops 2018-03-19 17:43:04 +01:00
N00byKing
0e72d0d826 More Warning cleanups 2018-03-19 17:27:04 +01:00
N00byKing
ef875d6a35 Clean Warnings (?) 2018-03-19 17:07:08 +01:00
bunnei
b2d7c92cae
Merge pull request #251 from Subv/tic_tsc 
GPU: Added TIC and TSC registers to the Maxwell3D register structure.
 2018-03-19 10:33:21 -04:00
Subv
dcae0c9a4f GPU: Added the TSC registers to the Maxwell3D register structure. 2018-03-19 00:36:25 -05:00
Subv
cff7b29bba GPU: Added the TIC registers to the Maxwell3D register structure. 2018-03-19 00:32:57 -05:00
bunnei
23a0d2d7b7
Merge pull request #193 from N00byKing/3184_2_robotic_boogaloo 
Implement Pull #3184 from citra: core/arm: Improve timing accuracy before service calls in JIT (Rebased)
 2018-03-18 22:35:47 -04:00
bunnei
2dc3a56e96
Merge pull request #250 from bunnei/buffer-dequeue-wait 
vi: TransactParcel DequeueBuffer should wait current thread
 2018-03-18 22:25:09 -04:00
bunnei
2332a44b68
Merge pull request #249 from Subv/macro_E1A 
GPU: Implement macro 0xE1A BindTextureInfoBuffer in HLE.
 2018-03-18 21:04:29 -04:00
bunnei
c1c92c30f9 vi: Remove DequeueBuffer and wait until next available buffer. 2018-03-18 20:56:35 -04:00
bunnei
c86af6939c hle_ipc: Add SleepClientThread to block current thread within HLE routines. 2018-03-18 20:56:34 -04:00
bunnei
2faa83ca13 hle_ipc: Use shared_ptr instead of unique_ptr to allow copies. 2018-03-18 20:56:33 -04:00
bunnei
019f1a0cf0 hle_ipc: Remove GetPointer(..) usage with WriteToOutgoingCommandBuffer. 2018-03-18 20:56:33 -04:00
bunnei
e353b9fb3d thread: Add THREADSTATUS_WAIT_HLE_EVENT, remove THREADSTATUS_WAIT_ARB. 2018-03-18 20:56:32 -04:00
Subv
03156d0c9a GPU: Implement macro 0xE1A BindTextureInfoBuffer in HLE. 
This macro simply sets the current CB_ADDRESS to the texture buffer address for the input shader stage.
 2018-03-18 19:03:40 -05:00
bunnei
6317a0b2ca
Merge pull request #248 from Subv/cb_data 
GPU: Handle writes to the CB_DATA method.
 2018-03-18 19:45:40 -04:00