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Maxwell3D: Rework the dirty system to be more consistant and scaleable
This commit is contained in:
parent
223a535f3f
commit
f2e7b29c14
10 changed files with 211 additions and 80 deletions
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@ -22,7 +22,7 @@ void DmaPusher::DispatchCalls() {
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MICROPROFILE_SCOPE(DispatchCalls);
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// On entering GPU code, assume all memory may be touched by the ARM core.
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gpu.Maxwell3D().dirty_flags.OnMemoryWrite();
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gpu.Maxwell3D().dirty.OnMemoryWrite();
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dma_pushbuffer_subindex = 0;
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@ -37,7 +37,7 @@ void KeplerCompute::CallMethod(const GPU::MethodCall& method_call) {
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const bool is_last_call = method_call.IsLastCall();
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upload_state.ProcessData(method_call.argument, is_last_call);
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if (is_last_call) {
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system.GPU().Maxwell3D().dirty_flags.OnMemoryWrite();
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system.GPU().Maxwell3D().dirty.OnMemoryWrite();
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}
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break;
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}
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@ -34,7 +34,7 @@ void KeplerMemory::CallMethod(const GPU::MethodCall& method_call) {
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const bool is_last_call = method_call.IsLastCall();
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upload_state.ProcessData(method_call.argument, is_last_call);
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if (is_last_call) {
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system.GPU().Maxwell3D().dirty_flags.OnMemoryWrite();
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system.GPU().Maxwell3D().dirty.OnMemoryWrite();
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}
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break;
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}
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@ -22,6 +22,7 @@ Maxwell3D::Maxwell3D(Core::System& system, VideoCore::RasterizerInterface& raste
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MemoryManager& memory_manager)
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: system{system}, rasterizer{rasterizer}, memory_manager{memory_manager},
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macro_interpreter{*this}, upload_state{memory_manager, regs.upload} {
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InitDirtySettings();
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InitializeRegisterDefaults();
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}
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@ -86,6 +87,80 @@ void Maxwell3D::InitializeRegisterDefaults() {
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regs.rt_separate_frag_data = 1;
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}
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#define DIRTY_REGS_POS(field_name) (offsetof(Maxwell3D::DirtyRegs, field_name))
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void Maxwell3D::InitDirtySettings() {
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const auto set_block = [this](const u32 start, const u32 range, const u8 position) {
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const u32 end = start + range;
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for (std::size_t i = start; i < end; i++) {
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dirty_pointers[i] = position;
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}
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};
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for (std::size_t i = 0; i < DirtyRegs::NUM_REGS; i++) {
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dirty.regs[i] = true;
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}
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// Init Render Targets
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constexpr u32 registers_per_rt = sizeof(regs.rt[0]) / sizeof(u32);
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constexpr u32 rt_start_reg = MAXWELL3D_REG_INDEX(rt);
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constexpr u32 rt_end_reg = rt_start_reg + registers_per_rt * 8;
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u32 rt_dirty_reg = DIRTY_REGS_POS(render_target);
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for (u32 rt_reg = rt_start_reg; rt_reg < rt_end_reg; rt_reg += registers_per_rt) {
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set_block(rt_reg, registers_per_rt, rt_dirty_reg);
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rt_dirty_reg++;
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}
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constexpr u32 depth_buffer_flag = DIRTY_REGS_POS(depth_buffer);
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dirty_pointers[MAXWELL3D_REG_INDEX(zeta_enable)] = depth_buffer_flag;
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dirty_pointers[MAXWELL3D_REG_INDEX(zeta_width)] = depth_buffer_flag;
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dirty_pointers[MAXWELL3D_REG_INDEX(zeta_height)] = depth_buffer_flag;
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constexpr u32 registers_in_zeta = sizeof(regs.zeta) / sizeof(u32);
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constexpr u32 zeta_reg = MAXWELL3D_REG_INDEX(zeta);
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set_block(zeta_reg, registers_in_zeta, depth_buffer_flag);
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// Init Vertex Arrays
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constexpr u32 vertex_array_start = MAXWELL3D_REG_INDEX(vertex_array);
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constexpr u32 vertex_array_size = sizeof(regs.vertex_array[0]) / sizeof(u32);
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constexpr u32 vertex_array_end = vertex_array_start + vertex_array_size * Regs::NumVertexArrays;
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u32 va_reg = DIRTY_REGS_POS(vertex_array);
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u32 vi_reg = DIRTY_REGS_POS(vertex_instance);
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for (u32 vertex_reg = vertex_array_start; vertex_reg < vertex_array_end;
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vertex_reg += vertex_array_size) {
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set_block(vertex_reg, 3, va_reg);
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// The divisor concerns vertex array instances
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dirty_pointers[vertex_reg + 3] = vi_reg;
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va_reg++;
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vi_reg++;
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}
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constexpr u32 vertex_limit_start = MAXWELL3D_REG_INDEX(vertex_array_limit);
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constexpr u32 vertex_limit_size = sizeof(regs.vertex_array_limit[0]) / sizeof(u32);
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constexpr u32 vertex_limit_end = vertex_limit_start + vertex_limit_size * Regs::NumVertexArrays;
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va_reg = DIRTY_REGS_POS(vertex_array);
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for (u32 vertex_reg = vertex_limit_start; vertex_reg < vertex_limit_end;
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vertex_reg += vertex_limit_size) {
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set_block(vertex_reg, vertex_limit_size, va_reg);
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va_reg++;
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}
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constexpr u32 vertex_instance_start = MAXWELL3D_REG_INDEX(instanced_arrays);
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constexpr u32 vertex_instance_size =
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sizeof(regs.instanced_arrays.is_instanced[0]) / sizeof(u32);
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constexpr u32 vertex_instance_end =
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vertex_instance_start + vertex_instance_size * Regs::NumVertexArrays;
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vi_reg = DIRTY_REGS_POS(vertex_instance);
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for (u32 vertex_reg = vertex_instance_start; vertex_reg < vertex_instance_end;
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vertex_reg += vertex_instance_size) {
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set_block(vertex_reg, vertex_instance_size, vi_reg);
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vi_reg++;
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}
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set_block(MAXWELL3D_REG_INDEX(vertex_attrib_format), regs.vertex_attrib_format.size(),
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DIRTY_REGS_POS(vertex_attrib_format));
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// Init Shaders
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constexpr u32 shader_registers_count =
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sizeof(regs.shader_config[0]) * Regs::MaxShaderProgram / sizeof(u32);
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set_block(MAXWELL3D_REG_INDEX(shader_config[0]), shader_registers_count,
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DIRTY_REGS_POS(shaders));
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}
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void Maxwell3D::CallMacroMethod(u32 method, std::vector<u32> parameters) {
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// Reset the current macro.
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executing_macro = 0;
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@ -143,49 +218,19 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) {
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if (regs.reg_array[method] != method_call.argument) {
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regs.reg_array[method] = method_call.argument;
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// Color buffers
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constexpr u32 first_rt_reg = MAXWELL3D_REG_INDEX(rt);
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constexpr u32 registers_per_rt = sizeof(regs.rt[0]) / sizeof(u32);
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if (method >= first_rt_reg &&
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method < first_rt_reg + registers_per_rt * Regs::NumRenderTargets) {
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const std::size_t rt_index = (method - first_rt_reg) / registers_per_rt;
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dirty_flags.color_buffer.set(rt_index);
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}
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// Zeta buffer
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constexpr u32 registers_in_zeta = sizeof(regs.zeta) / sizeof(u32);
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if (method == MAXWELL3D_REG_INDEX(zeta_enable) ||
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method == MAXWELL3D_REG_INDEX(zeta_width) ||
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method == MAXWELL3D_REG_INDEX(zeta_height) ||
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(method >= MAXWELL3D_REG_INDEX(zeta) &&
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method < MAXWELL3D_REG_INDEX(zeta) + registers_in_zeta)) {
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dirty_flags.zeta_buffer = true;
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}
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// Shader
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constexpr u32 shader_registers_count =
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sizeof(regs.shader_config[0]) * Regs::MaxShaderProgram / sizeof(u32);
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if (method >= MAXWELL3D_REG_INDEX(shader_config[0]) &&
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method < MAXWELL3D_REG_INDEX(shader_config[0]) + shader_registers_count) {
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dirty_flags.shaders = true;
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}
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// Vertex format
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if (method >= MAXWELL3D_REG_INDEX(vertex_attrib_format) &&
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method < MAXWELL3D_REG_INDEX(vertex_attrib_format) + regs.vertex_attrib_format.size()) {
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dirty_flags.vertex_attrib_format = true;
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}
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// Vertex buffer
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if (method >= MAXWELL3D_REG_INDEX(vertex_array) &&
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method < MAXWELL3D_REG_INDEX(vertex_array) + 4 * Regs::NumVertexArrays) {
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dirty_flags.vertex_array.set((method - MAXWELL3D_REG_INDEX(vertex_array)) >> 2);
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} else if (method >= MAXWELL3D_REG_INDEX(vertex_array_limit) &&
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method < MAXWELL3D_REG_INDEX(vertex_array_limit) + 2 * Regs::NumVertexArrays) {
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dirty_flags.vertex_array.set((method - MAXWELL3D_REG_INDEX(vertex_array_limit)) >> 1);
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} else if (method >= MAXWELL3D_REG_INDEX(instanced_arrays) &&
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method < MAXWELL3D_REG_INDEX(instanced_arrays) + Regs::NumVertexArrays) {
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dirty_flags.vertex_array.set(method - MAXWELL3D_REG_INDEX(instanced_arrays));
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std::size_t dirty_reg = dirty_pointers[method];
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if (dirty_reg) {
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dirty.regs[dirty_reg] = true;
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if (dirty_reg >= DIRTY_REGS_POS(vertex_array) &&
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dirty_reg < DIRTY_REGS_POS(vertex_array_buffers)) {
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dirty.vertex_array_buffers = true;
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} else if (dirty_reg >= DIRTY_REGS_POS(vertex_instance) &&
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dirty_reg < DIRTY_REGS_POS(vertex_instances)) {
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dirty.vertex_instances = true;
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} else if (dirty_reg >= DIRTY_REGS_POS(render_target) &&
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dirty_reg < DIRTY_REGS_POS(render_settings)) {
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dirty.render_settings = true;
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}
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}
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}
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@ -261,7 +306,7 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) {
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const bool is_last_call = method_call.IsLastCall();
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upload_state.ProcessData(method_call.argument, is_last_call);
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if (is_last_call) {
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dirty_flags.OnMemoryWrite();
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dirty.OnMemoryWrite();
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}
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break;
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}
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@ -333,7 +378,6 @@ void Maxwell3D::ProcessQueryGet() {
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query_result.timestamp = system.CoreTiming().GetTicks();
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memory_manager.WriteBlock(sequence_address, &query_result, sizeof(query_result));
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}
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dirty_flags.OnMemoryWrite();
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break;
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}
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default:
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@ -418,8 +462,6 @@ void Maxwell3D::ProcessCBData(u32 value) {
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rasterizer.InvalidateRegion(ToCacheAddr(ptr), sizeof(u32));
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memory_manager.Write<u32>(address, value);
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dirty_flags.OnMemoryWrite();
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// Increment the current buffer position.
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regs.const_buffer.cb_pos = regs.const_buffer.cb_pos + 4;
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}
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@ -1124,23 +1124,73 @@ public:
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State state{};
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struct DirtyFlags {
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std::bitset<8> color_buffer{0xFF};
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std::bitset<32> vertex_array{0xFFFFFFFF};
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struct DirtyRegs {
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static constexpr std::size_t NUM_REGS = 256;
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union {
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struct {
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bool null_dirty;
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// Vertex Attributes
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bool vertex_attrib_format;
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// Vertex Arrays
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std::array<bool, 32> vertex_array;
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bool vertex_attrib_format = true;
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bool zeta_buffer = true;
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bool shaders = true;
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bool vertex_array_buffers;
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// Vertex Instances
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std::array<bool, 32> vertex_instance;
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bool vertex_instances;
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// Render Targets
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std::array<bool, 8> render_target;
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bool depth_buffer;
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bool render_settings;
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// Shaders
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bool shaders;
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// State
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bool viewport;
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bool clip_enabled;
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bool clip_coefficient;
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bool cull_mode;
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bool primitive_restart;
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bool depth_test;
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bool stencil_test;
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bool blend_state;
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bool logic_op;
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bool fragment_color_clamp;
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bool multi_sample;
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bool scissor_test;
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bool transform_feedback;
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bool point;
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bool color_mask;
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bool polygon_offset;
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bool alpha_test;
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bool memory_general;
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};
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std::array<bool, NUM_REGS> regs;
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};
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void ResetVertexArrays() {
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std::fill(vertex_array.begin(), vertex_array.end(), true);
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vertex_array_buffers = true;
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}
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void ResetRenderTargets() {
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depth_buffer = true;
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std::fill(render_target.begin(), render_target.end(), true);
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render_settings = true;
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}
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void OnMemoryWrite() {
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zeta_buffer = true;
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shaders = true;
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color_buffer.set();
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vertex_array.set();
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memory_general = true;
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ResetRenderTargets();
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ResetVertexArrays();
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}
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};
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DirtyFlags dirty_flags;
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} dirty{};
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std::array<u8, Regs::NUM_REGS> dirty_pointers{};
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/// Reads a register value located at the input method address
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u32 GetRegisterValue(u32 method) const;
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/// Retrieves information about a specific TSC entry from the TSC buffer.
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Texture::TSCEntry GetTSCEntry(u32 tsc_index) const;
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void InitDirtySettings();
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/**
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* Call a macro on this engine.
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* @param method Method to call
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@ -58,7 +58,7 @@ void MaxwellDMA::HandleCopy() {
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}
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// All copies here update the main memory, so mark all rasterizer states as invalid.
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system.GPU().Maxwell3D().dirty_flags.OnMemoryWrite();
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system.GPU().Maxwell3D().dirty.OnMemoryWrite();
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if (regs.exec.is_dst_linear && regs.exec.is_src_linear) {
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// When the enable_2d bit is disabled, the copy is performed as if we were copying a 1D
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@ -124,10 +124,10 @@ GLuint RasterizerOpenGL::SetupVertexFormat() {
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auto& gpu = system.GPU().Maxwell3D();
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const auto& regs = gpu.regs;
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if (!gpu.dirty_flags.vertex_attrib_format) {
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if (!gpu.dirty.vertex_attrib_format) {
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return state.draw.vertex_array;
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}
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gpu.dirty_flags.vertex_attrib_format = false;
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gpu.dirty.vertex_attrib_format = false;
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MICROPROFILE_SCOPE(OpenGL_VAO);
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@ -181,7 +181,7 @@ GLuint RasterizerOpenGL::SetupVertexFormat() {
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}
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// Rebinding the VAO invalidates the vertex buffer bindings.
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gpu.dirty_flags.vertex_array.set();
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gpu.dirty.ResetVertexArrays();
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state.draw.vertex_array = vao_entry.handle;
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return vao_entry.handle;
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@ -189,17 +189,20 @@ GLuint RasterizerOpenGL::SetupVertexFormat() {
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void RasterizerOpenGL::SetupVertexBuffer(GLuint vao) {
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auto& gpu = system.GPU().Maxwell3D();
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const auto& regs = gpu.regs;
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if (gpu.dirty_flags.vertex_array.none())
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if (!gpu.dirty.vertex_array_buffers)
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return;
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gpu.dirty.vertex_array_buffers = false;
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const auto& regs = gpu.regs;
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MICROPROFILE_SCOPE(OpenGL_VB);
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// Upload all guest vertex arrays sequentially to our buffer
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for (u32 index = 0; index < Maxwell::NumVertexArrays; ++index) {
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if (!gpu.dirty_flags.vertex_array[index])
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if (!gpu.dirty.vertex_array[index])
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continue;
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gpu.dirty.vertex_array[index] = false;
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gpu.dirty.vertex_instance[index] = false;
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const auto& vertex_array = regs.vertex_array[index];
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if (!vertex_array.IsEnabled())
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@ -224,8 +227,32 @@ void RasterizerOpenGL::SetupVertexBuffer(GLuint vao) {
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glVertexArrayBindingDivisor(vao, index, 0);
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}
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}
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}
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gpu.dirty_flags.vertex_array.reset();
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void RasterizerOpenGL::SetupVertexInstances(GLuint vao) {
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auto& gpu = system.GPU().Maxwell3D();
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if (!gpu.dirty.vertex_instances)
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return;
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gpu.dirty.vertex_instances = false;
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const auto& regs = gpu.regs;
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// Upload all guest vertex arrays sequentially to our buffer
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for (u32 index = 0; index < Maxwell::NumVertexArrays; ++index) {
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if (!gpu.dirty.vertex_instance[index])
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continue;
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gpu.dirty.vertex_instance[index] = false;
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if (regs.instanced_arrays.IsInstancingEnabled(index) &&
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regs.vertex_array[index].divisor != 0) {
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// Enable vertex buffer instancing with the specified divisor.
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glVertexArrayBindingDivisor(vao, index, regs.vertex_array[index].divisor);
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} else {
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// Disable the vertex buffer instancing.
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glVertexArrayBindingDivisor(vao, index, 0);
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}
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}
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}
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GLintptr RasterizerOpenGL::SetupIndexBuffer() {
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@ -341,7 +368,7 @@ void RasterizerOpenGL::SetupShaders(GLenum primitive_mode) {
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SyncClipEnabled(clip_distances);
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gpu.dirty_flags.shaders = false;
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gpu.dirty.shaders = false;
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}
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std::size_t RasterizerOpenGL::CalculateVertexArraysSize() const {
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@ -424,13 +451,13 @@ std::pair<bool, bool> RasterizerOpenGL::ConfigureFramebuffers(
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const FramebufferConfigState fb_config_state{using_color_fb, using_depth_fb, preserve_contents,
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single_color_target};
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if (fb_config_state == current_framebuffer_config_state &&
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gpu.dirty_flags.color_buffer.none() && !gpu.dirty_flags.zeta_buffer) {
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if (fb_config_state == current_framebuffer_config_state && !gpu.dirty.render_settings) {
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// Only skip if the previous ConfigureFramebuffers call was from the same kind (multiple or
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// single color targets). This is done because the guest registers may not change but the
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// host framebuffer may contain different attachments
|
||||
return current_depth_stencil_usage;
|
||||
}
|
||||
gpu.dirty.render_settings = false;
|
||||
current_framebuffer_config_state = fb_config_state;
|
||||
|
||||
texture_cache.GuardRenderTargets(true);
|
||||
|
@ -661,6 +688,7 @@ void RasterizerOpenGL::DrawArrays() {
|
|||
|
||||
// Upload vertex and index data.
|
||||
SetupVertexBuffer(vao);
|
||||
SetupVertexInstances(vao);
|
||||
const GLintptr index_buffer_offset = SetupIndexBuffer();
|
||||
|
||||
// Setup draw parameters. It will automatically choose what glDraw* method to use.
|
||||
|
@ -687,7 +715,7 @@ void RasterizerOpenGL::DrawArrays() {
|
|||
|
||||
if (invalidate) {
|
||||
// As all cached buffers are invalidated, we need to recheck their state.
|
||||
gpu.dirty_flags.vertex_array.set();
|
||||
gpu.dirty.ResetVertexArrays();
|
||||
}
|
||||
|
||||
shader_program_manager->ApplyTo(state);
|
||||
|
@ -700,6 +728,7 @@ void RasterizerOpenGL::DrawArrays() {
|
|||
params.DispatchDraw();
|
||||
|
||||
accelerate_draw = AccelDraw::Disabled;
|
||||
gpu.dirty.memory_general = false;
|
||||
}
|
||||
|
||||
void RasterizerOpenGL::FlushAll() {}
|
||||
|
|
|
@ -216,6 +216,7 @@ private:
|
|||
GLuint SetupVertexFormat();
|
||||
|
||||
void SetupVertexBuffer(GLuint vao);
|
||||
void SetupVertexInstances(GLuint vao);
|
||||
|
||||
GLintptr SetupIndexBuffer();
|
||||
|
||||
|
|
|
@ -572,7 +572,7 @@ std::unordered_map<u64, UnspecializedShader> ShaderCacheOpenGL::GenerateUnspecia
|
|||
}
|
||||
|
||||
Shader ShaderCacheOpenGL::GetStageProgram(Maxwell::ShaderProgram program) {
|
||||
if (!system.GPU().Maxwell3D().dirty_flags.shaders) {
|
||||
if (!system.GPU().Maxwell3D().dirty.shaders) {
|
||||
return last_shaders[static_cast<std::size_t>(program)];
|
||||
}
|
||||
|
||||
|
|
|
@ -116,10 +116,10 @@ public:
|
|||
std::lock_guard lock{mutex};
|
||||
auto& maxwell3d = system.GPU().Maxwell3D();
|
||||
|
||||
if (!maxwell3d.dirty_flags.zeta_buffer) {
|
||||
if (!maxwell3d.dirty.depth_buffer) {
|
||||
return depth_buffer.view;
|
||||
}
|
||||
maxwell3d.dirty_flags.zeta_buffer = false;
|
||||
maxwell3d.dirty.depth_buffer = false;
|
||||
|
||||
const auto& regs{maxwell3d.regs};
|
||||
const auto gpu_addr{regs.zeta.Address()};
|
||||
|
@ -145,10 +145,10 @@ public:
|
|||
std::lock_guard lock{mutex};
|
||||
ASSERT(index < Tegra::Engines::Maxwell3D::Regs::NumRenderTargets);
|
||||
auto& maxwell3d = system.GPU().Maxwell3D();
|
||||
if (!maxwell3d.dirty_flags.color_buffer[index]) {
|
||||
if (!maxwell3d.dirty.render_target[index]) {
|
||||
return render_targets[index].view;
|
||||
}
|
||||
maxwell3d.dirty_flags.color_buffer.reset(index);
|
||||
maxwell3d.dirty.render_target[index] = false;
|
||||
|
||||
const auto& regs{maxwell3d.regs};
|
||||
if (index >= regs.rt_control.count || regs.rt[index].Address() == 0 ||
|
||||
|
@ -272,12 +272,19 @@ protected:
|
|||
|
||||
void ManageRenderTargetUnregister(TSurface& surface) {
|
||||
auto& maxwell3d = system.GPU().Maxwell3D();
|
||||
<<<<<<< HEAD
|
||||
const u32 index = surface->GetRenderTarget();
|
||||
if (index == DEPTH_RT) {
|
||||
maxwell3d.dirty_flags.zeta_buffer = true;
|
||||
=======
|
||||
u32 index = surface->GetRenderTarget();
|
||||
if (index == 8) {
|
||||
maxwell3d.dirty.depth_buffer = true;
|
||||
>>>>>>> Maxwell3D: Rework the dirty system to be more consistant and scaleable
|
||||
} else {
|
||||
maxwell3d.dirty_flags.color_buffer.set(index, true);
|
||||
maxwell3d.dirty.render_target[index] = true;
|
||||
}
|
||||
maxwell3d.dirty.render_settings = true;
|
||||
}
|
||||
|
||||
void Register(TSurface surface) {
|
||||
|
|
Loading…
Reference in a new issue