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shader/arithmetic: Implement FCMP
Compares the third operand with zero, then selects between the first and second.
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05df4a8c94
commit
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2 changed files with 17 additions and 1 deletions
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@ -1095,6 +1095,11 @@ union Instruction {
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BitField<55, 1, u64> ftz;
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BitField<55, 1, u64> ftz;
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} fset;
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} fset;
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union {
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BitField<47, 1, u64> ftz;
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BitField<48, 4, PredCondition> cond;
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} fcmp;
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union {
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union {
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BitField<49, 1, u64> bf;
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BitField<49, 1, u64> bf;
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BitField<35, 3, PredCondition> cond;
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BitField<35, 3, PredCondition> cond;
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@ -1771,6 +1776,7 @@ public:
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ICMP_R,
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ICMP_R,
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ICMP_CR,
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ICMP_CR,
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ICMP_IMM,
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ICMP_IMM,
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FCMP_R,
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MUFU, // Multi-Function Operator
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MUFU, // Multi-Function Operator
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RRO_C, // Range Reduction Operator
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RRO_C, // Range Reduction Operator
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RRO_R,
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RRO_R,
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@ -2074,6 +2080,7 @@ private:
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INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP2_R"),
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INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP2_R"),
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INST("0111111-0-------", Id::HSETP2_IMM, Type::HalfSetPredicate, "HSETP2_IMM"),
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INST("0111111-0-------", Id::HSETP2_IMM, Type::HalfSetPredicate, "HSETP2_IMM"),
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INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"),
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INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"),
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INST("010110111010----", Id::FCMP_R, Type::Arithmetic, "FCMP_R"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
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INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
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@ -21,7 +21,7 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) {
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Node op_a = GetRegister(instr.gpr8);
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Node op_a = GetRegister(instr.gpr8);
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Node op_b = [&]() -> Node {
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Node op_b = [&] {
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if (instr.is_b_imm) {
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if (instr.is_b_imm) {
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return GetImmediate19(instr);
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return GetImmediate19(instr);
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} else if (instr.is_b_gpr) {
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} else if (instr.is_b_gpr) {
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@ -141,6 +141,15 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) {
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SetRegister(bb, instr.gpr0, value);
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SetRegister(bb, instr.gpr0, value);
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break;
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break;
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}
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}
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case OpCode::Id::FCMP_R: {
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UNIMPLEMENTED_IF(instr.fcmp.ftz == 0);
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Node op_c = GetRegister(instr.gpr39);
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Node comp = GetPredicateComparisonFloat(instr.fcmp.cond, std::move(op_c), Immediate(0.0f));
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SetRegister(
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bb, instr.gpr0,
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Operation(OperationCode::Select, std::move(comp), std::move(op_a), std::move(op_b)));
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break;
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}
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case OpCode::Id::RRO_C:
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case OpCode::Id::RRO_C:
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case OpCode::Id::RRO_R:
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case OpCode::Id::RRO_R:
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case OpCode::Id::RRO_IMM: {
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case OpCode::Id::RRO_IMM: {
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