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arithmetic_integer_immediate: Make use of std::move where applicable
Same behavior, minus any redundant atomic reference count increments and decrements.
This commit is contained in:
parent
2b863c9aa3
commit
e3a615a616
1 changed files with 19 additions and 16 deletions
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@ -28,23 +28,26 @@ u32 ShaderIR::DecodeArithmeticIntegerImmediate(NodeBlock& bb, u32 pc) {
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case OpCode::Id::IADD32I: {
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case OpCode::Id::IADD32I: {
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UNIMPLEMENTED_IF_MSG(instr.iadd32i.saturate, "IADD32I saturation is not implemented");
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UNIMPLEMENTED_IF_MSG(instr.iadd32i.saturate, "IADD32I saturation is not implemented");
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op_a = GetOperandAbsNegInteger(op_a, false, instr.iadd32i.negate_a, true);
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op_a = GetOperandAbsNegInteger(std::move(op_a), false, instr.iadd32i.negate_a != 0, true);
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const Node value = Operation(OperationCode::IAdd, PRECISE, op_a, op_b);
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Node value = Operation(OperationCode::IAdd, PRECISE, std::move(op_a), std::move(op_b));
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SetInternalFlagsFromInteger(bb, value, instr.op_32.generates_cc);
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SetInternalFlagsFromInteger(bb, value, instr.op_32.generates_cc != 0);
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SetRegister(bb, instr.gpr0, value);
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SetRegister(bb, instr.gpr0, std::move(value));
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break;
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break;
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}
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}
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case OpCode::Id::LOP32I: {
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case OpCode::Id::LOP32I: {
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if (instr.alu.lop32i.invert_a)
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if (instr.alu.lop32i.invert_a) {
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op_a = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_a);
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op_a = Operation(OperationCode::IBitwiseNot, NO_PRECISE, std::move(op_a));
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}
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if (instr.alu.lop32i.invert_b)
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if (instr.alu.lop32i.invert_b) {
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op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_b);
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op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, std::move(op_b));
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}
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WriteLogicOperation(bb, instr.gpr0, instr.alu.lop32i.operation, op_a, op_b,
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WriteLogicOperation(bb, instr.gpr0, instr.alu.lop32i.operation, std::move(op_a),
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PredicateResultMode::None, Pred::UnusedIndex, instr.op_32.generates_cc);
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std::move(op_b), PredicateResultMode::None, Pred::UnusedIndex,
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instr.op_32.generates_cc != 0);
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break;
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break;
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}
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}
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default:
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default:
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@ -58,14 +61,14 @@ u32 ShaderIR::DecodeArithmeticIntegerImmediate(NodeBlock& bb, u32 pc) {
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void ShaderIR::WriteLogicOperation(NodeBlock& bb, Register dest, LogicOperation logic_op, Node op_a,
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void ShaderIR::WriteLogicOperation(NodeBlock& bb, Register dest, LogicOperation logic_op, Node op_a,
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Node op_b, PredicateResultMode predicate_mode, Pred predicate,
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Node op_b, PredicateResultMode predicate_mode, Pred predicate,
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bool sets_cc) {
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bool sets_cc) {
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const Node result = [&]() {
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Node result = [&] {
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switch (logic_op) {
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switch (logic_op) {
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case LogicOperation::And:
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case LogicOperation::And:
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return Operation(OperationCode::IBitwiseAnd, PRECISE, op_a, op_b);
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return Operation(OperationCode::IBitwiseAnd, PRECISE, std::move(op_a), std::move(op_b));
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case LogicOperation::Or:
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case LogicOperation::Or:
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return Operation(OperationCode::IBitwiseOr, PRECISE, op_a, op_b);
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return Operation(OperationCode::IBitwiseOr, PRECISE, std::move(op_a), std::move(op_b));
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case LogicOperation::Xor:
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case LogicOperation::Xor:
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return Operation(OperationCode::IBitwiseXor, PRECISE, op_a, op_b);
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return Operation(OperationCode::IBitwiseXor, PRECISE, std::move(op_a), std::move(op_b));
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case LogicOperation::PassB:
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case LogicOperation::PassB:
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return op_b;
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return op_b;
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default:
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default:
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@ -84,8 +87,8 @@ void ShaderIR::WriteLogicOperation(NodeBlock& bb, Register dest, LogicOperation
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return;
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return;
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case PredicateResultMode::NotZero: {
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case PredicateResultMode::NotZero: {
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// Set the predicate to true if the result is not zero.
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// Set the predicate to true if the result is not zero.
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const Node compare = Operation(OperationCode::LogicalINotEqual, result, Immediate(0));
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Node compare = Operation(OperationCode::LogicalINotEqual, std::move(result), Immediate(0));
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SetPredicate(bb, static_cast<u64>(predicate), compare);
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SetPredicate(bb, static_cast<u64>(predicate), std::move(compare));
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break;
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break;
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}
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}
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default:
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default:
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