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Merge pull request #9406 from vonchenplus/topology
video_core: Adjust topology update logic and Adjust Clear Manage
This commit is contained in:
commit
da58eb6208
4 changed files with 36 additions and 32 deletions
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@ -46,21 +46,26 @@ void DrawManager::ProcessMethodCall(u32 method, u32 argument) {
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SetInlineIndexBuffer(regs.inline_index_4x8.index2);
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SetInlineIndexBuffer(regs.inline_index_4x8.index2);
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SetInlineIndexBuffer(regs.inline_index_4x8.index3);
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SetInlineIndexBuffer(regs.inline_index_4x8.index3);
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break;
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break;
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case MAXWELL3D_REG_INDEX(topology_override):
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case MAXWELL3D_REG_INDEX(vertex_array_instance_first):
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use_topology_override = true;
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case MAXWELL3D_REG_INDEX(vertex_array_instance_subsequent): {
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LOG_WARNING(HW_GPU, "(STUBBED) called");
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break;
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break;
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}
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default:
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default:
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break;
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break;
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}
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}
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}
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}
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void DrawManager::Clear(u32 layer_count) {
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void DrawManager::Clear(u32 layer_count) {
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if (maxwell3d->ShouldExecute()) {
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maxwell3d->rasterizer->Clear(layer_count);
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maxwell3d->rasterizer->Clear(layer_count);
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}
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}
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}
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void DrawManager::DrawDeferred() {
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void DrawManager::DrawDeferred() {
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if (draw_state.draw_mode != DrawMode::Instance || draw_state.instance_count == 0)
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if (draw_state.draw_mode != DrawMode::Instance || draw_state.instance_count == 0) {
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return;
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return;
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}
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DrawEnd(draw_state.instance_count + 1, true);
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DrawEnd(draw_state.instance_count + 1, true);
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draw_state.instance_count = 0;
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draw_state.instance_count = 0;
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}
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}
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@ -115,8 +120,9 @@ void DrawManager::DrawEnd(u32 instance_count, bool force_draw) {
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const auto& regs{maxwell3d->regs};
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const auto& regs{maxwell3d->regs};
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switch (draw_state.draw_mode) {
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switch (draw_state.draw_mode) {
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case DrawMode::Instance:
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case DrawMode::Instance:
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if (!force_draw)
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if (!force_draw) {
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break;
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break;
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}
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[[fallthrough]];
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[[fallthrough]];
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case DrawMode::General:
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case DrawMode::General:
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draw_state.base_instance = regs.global_base_instance_index;
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draw_state.base_instance = regs.global_base_instance_index;
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@ -156,11 +162,12 @@ void DrawManager::DrawIndexSmall(u32 argument) {
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ProcessDraw(true, 1);
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ProcessDraw(true, 1);
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}
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}
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void DrawManager::ProcessTopologyOverride() {
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void DrawManager::UpdateTopology() {
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if (!use_topology_override)
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return;
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const auto& regs{maxwell3d->regs};
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const auto& regs{maxwell3d->regs};
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switch (regs.primitive_topology_control) {
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case PrimitiveTopologyControl::UseInBeginMethods:
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break;
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case PrimitiveTopologyControl::UseSeparateState:
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switch (regs.topology_override) {
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switch (regs.topology_override) {
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case PrimitiveTopologyOverride::None:
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case PrimitiveTopologyOverride::None:
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break;
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break;
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@ -177,15 +184,18 @@ void DrawManager::ProcessTopologyOverride() {
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draw_state.topology = static_cast<PrimitiveTopology>(regs.topology_override);
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draw_state.topology = static_cast<PrimitiveTopology>(regs.topology_override);
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break;
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break;
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}
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}
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break;
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}
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}
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}
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void DrawManager::ProcessDraw(bool draw_indexed, u32 instance_count) {
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void DrawManager::ProcessDraw(bool draw_indexed, u32 instance_count) {
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LOG_TRACE(HW_GPU, "called, topology={}, count={}", draw_state.topology,
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LOG_TRACE(HW_GPU, "called, topology={}, count={}", draw_state.topology,
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draw_indexed ? draw_state.index_buffer.count : draw_state.vertex_buffer.count);
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draw_indexed ? draw_state.index_buffer.count : draw_state.vertex_buffer.count);
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ProcessTopologyOverride();
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UpdateTopology();
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if (maxwell3d->ShouldExecute())
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if (maxwell3d->ShouldExecute()) {
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maxwell3d->rasterizer->Draw(draw_indexed, instance_count);
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maxwell3d->rasterizer->Draw(draw_indexed, instance_count);
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}
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}
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}
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} // namespace Tegra::Engines
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} // namespace Tegra::Engines
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@ -10,6 +10,7 @@ class RasterizerInterface;
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}
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}
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namespace Tegra::Engines {
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namespace Tegra::Engines {
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using PrimitiveTopologyControl = Maxwell3D::Regs::PrimitiveTopologyControl;
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using PrimitiveTopology = Maxwell3D::Regs::PrimitiveTopology;
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using PrimitiveTopology = Maxwell3D::Regs::PrimitiveTopology;
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using PrimitiveTopologyOverride = Maxwell3D::Regs::PrimitiveTopologyOverride;
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using PrimitiveTopologyOverride = Maxwell3D::Regs::PrimitiveTopologyOverride;
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using IndexBuffer = Maxwell3D::Regs::IndexBuffer;
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using IndexBuffer = Maxwell3D::Regs::IndexBuffer;
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@ -58,12 +59,11 @@ private:
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void DrawIndexSmall(u32 argument);
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void DrawIndexSmall(u32 argument);
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void ProcessTopologyOverride();
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void UpdateTopology();
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void ProcessDraw(bool draw_indexed, u32 instance_count);
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void ProcessDraw(bool draw_indexed, u32 instance_count);
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Maxwell3D* maxwell3d{};
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Maxwell3D* maxwell3d{};
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State draw_state{};
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State draw_state{};
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bool use_topology_override{};
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};
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};
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} // namespace Tegra::Engines
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} // namespace Tegra::Engines
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@ -138,9 +138,6 @@ void RasterizerOpenGL::LoadDiskResources(u64 title_id, std::stop_token stop_load
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void RasterizerOpenGL::Clear(u32 layer_count) {
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void RasterizerOpenGL::Clear(u32 layer_count) {
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MICROPROFILE_SCOPE(OpenGL_Clears);
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MICROPROFILE_SCOPE(OpenGL_Clears);
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if (!maxwell3d->ShouldExecute()) {
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return;
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}
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const auto& regs = maxwell3d->regs;
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const auto& regs = maxwell3d->regs;
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bool use_color{};
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bool use_color{};
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@ -216,9 +216,6 @@ void RasterizerVulkan::Draw(bool is_indexed, u32 instance_count) {
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void RasterizerVulkan::Clear(u32 layer_count) {
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void RasterizerVulkan::Clear(u32 layer_count) {
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MICROPROFILE_SCOPE(Vulkan_Clearing);
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MICROPROFILE_SCOPE(Vulkan_Clearing);
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if (!maxwell3d->ShouldExecute()) {
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return;
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}
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FlushWork();
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FlushWork();
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query_cache.UpdateCounters();
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query_cache.UpdateCounters();
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