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dyncom: Implement QADD/QSUB/QDADD/QDSUB
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parent
b058ce6feb
commit
d00c22c706
4 changed files with 117 additions and 25 deletions
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@ -2053,7 +2053,37 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(pld)(unsigned int inst, int index)
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QADD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->op1 = BITS(inst, 21, 22);
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inst_cream->Rm = BITS(inst, 0, 3);
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inst_cream->Rn = BITS(inst, 16, 19);
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inst_cream->Rd = BITS(inst, 12, 15);
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd8)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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@ -2080,9 +2110,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(qaddsubx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QDADD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QDSUB"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QSUB"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub8)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd8)(inst, index);
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@ -5042,6 +5069,78 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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QADD_INST:
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QDADD_INST:
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QDSUB_INST:
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QSUB_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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const u8 op1 = inst_cream->op1;
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const u32 rm_val = RM;
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const u32 rn_val = RN;
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u32 result = 0;
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// QADD
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if (op1 == 0x00) {
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result = rm_val + rn_val;
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if (AddOverflow(rm_val, rn_val, result)) {
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result = POS(result) ? 0x80000000 : 0x7FFFFFFF;
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cpu->Cpsr |= (1 << 27);
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}
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}
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// QSUB
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else if (op1 == 0x01) {
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result = rm_val - rn_val;
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if (SubOverflow(rm_val, rn_val, result)) {
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result = POS(result) ? 0x80000000 : 0x7FFFFFFF;
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cpu->Cpsr |= (1 << 27);
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}
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}
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// QDADD
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else if (op1 == 0x02) {
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u32 mul = (rn_val * 2);
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if (AddOverflow(rn_val, rn_val, rn_val * 2)) {
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mul = POS(mul) ? 0x80000000 : 0x7FFFFFFF;
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cpu->Cpsr |= (1 << 27);
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}
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result = mul + rm_val;
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if (AddOverflow(rm_val, mul, result)) {
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result = POS(result) ? 0x80000000 : 0x7FFFFFFF;
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cpu->Cpsr |= (1 << 27);
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}
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}
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// QDSUB
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else if (op1 == 0x03) {
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u32 mul = (rn_val * 2);
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if (AddOverflow(rn_val, rn_val, mul)) {
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mul = POS(mul) ? 0x80000000 : 0x7FFFFFFF;
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cpu->Cpsr |= (1 << 27);
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}
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result = rm_val - mul;
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if (SubOverflow(rm_val, mul, result)) {
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result = POS(result) ? 0x80000000 : 0x7FFFFFFF;
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cpu->Cpsr |= (1 << 27);
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}
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}
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RD = result;
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(generic_arm_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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QADD8_INST:
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QADD16_INST:
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QADDSUBX_INST:
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@ -5104,10 +5203,6 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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GOTO_NEXT_INST;
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}
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QDADD_INST:
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QDSUB_INST:
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QSUB_INST:
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REV_INST:
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REV16_INST:
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REVSH_INST:
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@ -418,22 +418,18 @@ ARMul_NegZero (ARMul_State * state, ARMword result)
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}
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}
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/* Compute whether an addition of A and B, giving RESULT, overflowed. */
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int
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AddOverflow (ARMword a, ARMword b, ARMword result)
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// Compute whether an addition of A and B, giving RESULT, overflowed.
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bool AddOverflow(ARMword a, ARMword b, ARMword result)
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{
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return ((NEG (a) && NEG (b) && POS (result))
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|| (POS (a) && POS (b) && NEG (result)));
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return ((NEG(a) && NEG(b) && POS(result)) ||
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(POS(a) && POS(b) && NEG(result)));
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}
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/* Compute whether a subtraction of A and B, giving RESULT, overflowed. */
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int
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SubOverflow (ARMword a, ARMword b, ARMword result)
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// Compute whether a subtraction of A and B, giving RESULT, overflowed.
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bool SubOverflow(ARMword a, ARMword b, ARMword result)
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{
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return ((NEG (a) && POS (b) && POS (result))
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|| (POS (a) && NEG (b) && NEG (result)));
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return ((NEG(a) && POS(b) && POS(result)) ||
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(POS(a) && NEG(b) && NEG(result)));
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}
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/* Assigns the C flag after an addition of a and b to give result. */
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@ -70,6 +70,9 @@
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#define DATACACHE 1
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#define INSTCACHE 2
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#define POS(i) ( (~(i)) >> 31 )
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#define NEG(i) ( (i) >> 31 )
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#ifndef __STDC__
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typedef char *VoidStar;
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#endif
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@ -783,6 +786,8 @@ RUn %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x\n",\
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//#define PXA250 0x69052903
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// 0x69052903; //PXA250 B1 from intel 278522-001.pdf
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extern bool AddOverflow(ARMword, ARMword, ARMword);
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extern bool SubOverflow(ARMword, ARMword, ARMword);
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extern void ARMul_UndefInstr(ARMul_State*, ARMword);
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extern void ARMul_FixCPSR(ARMul_State*, ARMword, ARMword);
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@ -42,9 +42,6 @@
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#define R15FBIT (1L << 26)
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#define R15IFBITS (3L << 26)
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#define POS(i) ( (~(i)) >> 31 )
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#define NEG(i) ( (i) >> 31 )
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#ifdef MODET /* Thumb support. */
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/* ??? This bit is actually in the low order bit of the PC in the hardware.
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It isn't clear if the simulator needs to model that or not. */
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@ -561,8 +558,7 @@ tdstate;
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/* Prototypes for exported functions. */
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extern unsigned ARMul_NthReg (ARMword, unsigned);
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extern int AddOverflow (ARMword, ARMword, ARMword);
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extern int SubOverflow (ARMword, ARMword, ARMword);
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/* Prototypes for exported functions. */
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#ifdef __cplusplus
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extern "C" {
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