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GPU: Basic implementation of the Kepler Inline Memory engine (p2mf).
This engine writes data from a FIFO register into the configured address.
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6 changed files with 146 additions and 0 deletions
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@ -5,6 +5,8 @@ add_library(video_core STATIC
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debug_utils/debug_utils.h
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engines/fermi_2d.cpp
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engines/fermi_2d.h
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engines/kepler_memory.cpp
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engines/kepler_memory.h
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engines/maxwell_3d.cpp
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engines/maxwell_3d.h
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engines/maxwell_compute.cpp
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@ -14,6 +14,7 @@
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#include "core/tracer/recorder.h"
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#include "video_core/command_processor.h"
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/engines/kepler_memory.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_compute.h"
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#include "video_core/engines/maxwell_dma.h"
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@ -69,6 +70,9 @@ void GPU::ProcessCommandLists(const std::vector<CommandListHeader>& commands) {
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case EngineID::MAXWELL_DMA_COPY_A:
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maxwell_dma->WriteReg(method, value);
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break;
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case EngineID::KEPLER_INLINE_TO_MEMORY_B:
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kepler_memory->WriteReg(method, value);
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break;
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default:
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UNIMPLEMENTED_MSG("Unimplemented engine");
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}
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45
src/video_core/engines/kepler_memory.cpp
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45
src/video_core/engines/kepler_memory.cpp
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@ -0,0 +1,45 @@
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/logging/log.h"
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#include "core/memory.h"
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#include "video_core/engines/kepler_memory.h"
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namespace Tegra::Engines {
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KeplerMemory::KeplerMemory(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
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KeplerMemory::~KeplerMemory() = default;
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void KeplerMemory::WriteReg(u32 method, u32 value) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid KeplerMemory register, increase the size of the Regs structure");
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regs.reg_array[method] = value;
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switch (method) {
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case KEPLERMEMORY_REG_INDEX(exec): {
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state.write_offset = 0;
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break;
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}
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case KEPLERMEMORY_REG_INDEX(data): {
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ProcessData(value);
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break;
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}
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}
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}
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void KeplerMemory::ProcessData(u32 data) {
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ASSERT_MSG(regs.exec.linear, "Non-linear uploads are not supported");
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ASSERT(regs.dest.x == 0 && regs.dest.y == 0 && regs.dest.z == 0);
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GPUVAddr address = regs.dest.Address();
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VAddr dest_address =
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*memory_manager.GpuToCpuAddress(address + state.write_offset * sizeof(u32));
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Memory::Write32(dest_address, data);
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state.write_offset++;
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}
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} // namespace Tegra::Engines
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90
src/video_core/engines/kepler_memory.h
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90
src/video_core/engines/kepler_memory.h
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@ -0,0 +1,90 @@
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/memory_manager.h"
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namespace Tegra::Engines {
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#define KEPLERMEMORY_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::KeplerMemory::Regs, field_name) / sizeof(u32))
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class KeplerMemory final {
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public:
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KeplerMemory(MemoryManager& memory_manager);
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~KeplerMemory();
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value);
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struct Regs {
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static constexpr size_t NUM_REGS = 0x7F;
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union {
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struct {
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INSERT_PADDING_WORDS(0x60);
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u32 line_length_in;
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u32 line_count;
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struct {
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u32 address_high;
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u32 address_low;
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u32 pitch;
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u32 block_dimensions;
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u32 width;
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u32 height;
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u32 depth;
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u32 z;
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u32 x;
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u32 y;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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} dest;
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struct {
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union {
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BitField<0, 1, u32> linear;
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};
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} exec;
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u32 data;
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INSERT_PADDING_WORDS(0x11);
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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struct {
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u32 write_offset = 0;
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} state{};
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private:
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MemoryManager& memory_manager;
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void ProcessData(u32 data);
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(KeplerMemory::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(line_length_in, 0x60);
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ASSERT_REG_POSITION(line_count, 0x61);
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ASSERT_REG_POSITION(dest, 0x62);
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ASSERT_REG_POSITION(exec, 0x6C);
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ASSERT_REG_POSITION(data, 0x6D);
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#undef ASSERT_REG_POSITION
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} // namespace Tegra::Engines
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@ -4,6 +4,7 @@
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#include "common/assert.h"
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/engines/kepler_memory.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_compute.h"
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#include "video_core/engines/maxwell_dma.h"
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@ -27,6 +28,7 @@ GPU::GPU(VideoCore::RasterizerInterface& rasterizer) {
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fermi_2d = std::make_unique<Engines::Fermi2D>(*memory_manager);
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maxwell_compute = std::make_unique<Engines::MaxwellCompute>();
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maxwell_dma = std::make_unique<Engines::MaxwellDMA>(*memory_manager);
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kepler_memory = std::make_unique<Engines::KeplerMemory>(*memory_manager);
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}
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GPU::~GPU() = default;
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@ -102,6 +102,7 @@ class Fermi2D;
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class Maxwell3D;
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class MaxwellCompute;
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class MaxwellDMA;
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class KeplerMemory;
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} // namespace Engines
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enum class EngineID {
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@ -146,6 +147,8 @@ private:
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std::unique_ptr<Engines::MaxwellCompute> maxwell_compute;
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/// DMA engine
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std::unique_ptr<Engines::MaxwellDMA> maxwell_dma;
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/// Inline memory engine
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std::unique_ptr<Engines::KeplerMemory> kepler_memory;
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};
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} // namespace Tegra
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