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Dyncom: Move cream cache to ARMul_State.
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parent
c7dc799e19
commit
bab5abaf46
4 changed files with 18 additions and 25 deletions
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@ -2,6 +2,8 @@
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// Licensed under GPLv2 or any later version
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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// Refer to the license.txt file included.
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#include "common/make_unique.h"
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#include "core/arm/skyeye_common/armemu.h"
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#include "core/arm/skyeye_common/armemu.h"
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#include "core/arm/skyeye_common/vfp/vfp.h"
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#include "core/arm/skyeye_common/vfp/vfp.h"
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@ -17,7 +19,7 @@ const static cpu_config_t s_arm11_cpu_info = {
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};
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};
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ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
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ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
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state = std::unique_ptr<ARMul_State>(new ARMul_State);
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state = Common::make_unique<ARMul_State>();
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ARMul_NewState(state.get());
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ARMul_NewState(state.get());
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ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
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ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
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@ -6,7 +6,6 @@
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#include <algorithm>
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#include <algorithm>
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#include <cstdio>
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#include <cstdio>
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#include <unordered_map>
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#include "common/logging/log.h"
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#include "common/logging/log.h"
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#include "common/profiler.h"
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#include "common/profiler.h"
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@ -3533,25 +3532,6 @@ const transop_fp_t arm_instruction_trans[] = {
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INTERPRETER_TRANSLATE(blx_1_thumb)
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INTERPRETER_TRANSLATE(blx_1_thumb)
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};
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};
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typedef std::unordered_map<u32, int> bb_map;
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static bb_map CreamCache;
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static void insert_bb(unsigned int addr, int start) {
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CreamCache[addr] = start;
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}
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static int find_bb(unsigned int addr, int& start) {
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int ret = -1;
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bb_map::const_iterator it = CreamCache.find(addr);
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if (it != CreamCache.end()) {
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start = static_cast<int>(it->second);
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ret = 0;
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} else {
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ret = -1;
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}
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return ret;
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}
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enum {
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enum {
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FETCH_SUCCESS,
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FETCH_SUCCESS,
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FETCH_FAILURE
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FETCH_FAILURE
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@ -3674,7 +3654,9 @@ translated:
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}
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}
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ret = inst_base->br;
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ret = inst_base->br;
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};
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};
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insert_bb(pc_start, bb_start);
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cpu->instruction_cache[pc_start] = bb_start;
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return KEEP_GOING;
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return KEEP_GOING;
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}
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}
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@ -4001,9 +3983,14 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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phys_addr = cpu->Reg[15];
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phys_addr = cpu->Reg[15];
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if (find_bb(cpu->Reg[15], ptr) == -1)
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// Find the cached instruction cream, otherwise translate it...
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auto itr = cpu->instruction_cache.find(cpu->Reg[15]);
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if (itr != cpu->instruction_cache.end()) {
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ptr = itr->second;
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} else {
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if (InterpreterTranslate(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
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if (InterpreterTranslate(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
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goto END;
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goto END;
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}
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inst_base = (arm_inst *)&inst_buf[ptr];
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inst_base = (arm_inst *)&inst_buf[ptr];
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GOTO_NEXT_INST;
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GOTO_NEXT_INST;
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@ -26,8 +26,6 @@
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\***************************************************************************/
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\***************************************************************************/
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ARMul_State* ARMul_NewState(ARMul_State* state)
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ARMul_State* ARMul_NewState(ARMul_State* state)
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{
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{
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memset(state, 0, sizeof(ARMul_State));
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state->Emulate = RUN;
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state->Emulate = RUN;
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state->Mode = USER32MODE;
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state->Mode = USER32MODE;
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@ -17,6 +17,8 @@
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#pragma once
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#pragma once
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#include <unordered_map>
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#include "common/common_types.h"
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#include "common/common_types.h"
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#include "core/arm/skyeye_common/arm_regformat.h"
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#include "core/arm/skyeye_common/arm_regformat.h"
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#include "core/arm/skyeye_common/skyeye_defs.h"
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#include "core/arm/skyeye_common/skyeye_defs.h"
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@ -152,6 +154,10 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
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// Added by ksh in 2005-10-1
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// Added by ksh in 2005-10-1
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cpu_config_t* cpu;
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cpu_config_t* cpu;
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// TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per
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// process for our purposes), not per ARMul_State (which tracks CPU core state).
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std::unordered_map<u32, int> instruction_cache;
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};
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};
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/***************************************************************************\
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/***************************************************************************\
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