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Merge pull request #9084 from vonchenplus/dma_copy
video_core: implement 1D copies based on VMM 'kind'
This commit is contained in:
Fernando S
GitHub
commit
b8a70c9999
7 changed files with 415 additions and 73 deletions
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@ -311,7 +311,8 @@ NvResult nvhost_as_gpu::Remap(const std::vector<u8>& input, std::vector<u8>& out
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handle->address +
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(static_cast<u64>(entry.handle_offset_big_pages) << vm.big_page_size_bits))};
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gmmu->Map(virtual_address, cpu_address, size, use_big_pages);
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gmmu->Map(virtual_address, cpu_address, size, static_cast<Tegra::PTEKind>(entry.kind),
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use_big_pages);
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}
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}
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@ -350,7 +351,8 @@ NvResult nvhost_as_gpu::MapBufferEx(const std::vector<u8>& input, std::vector<u8
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u64 gpu_address{static_cast<u64>(params.offset + params.buffer_offset)};
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VAddr cpu_address{mapping->ptr + params.buffer_offset};
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gmmu->Map(gpu_address, cpu_address, params.mapping_size, mapping->big_page);
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gmmu->Map(gpu_address, cpu_address, params.mapping_size,
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static_cast<Tegra::PTEKind>(params.kind), mapping->big_page);
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return NvResult::Success;
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} catch (const std::out_of_range&) {
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@ -389,7 +391,8 @@ NvResult nvhost_as_gpu::MapBufferEx(const std::vector<u8>& input, std::vector<u8
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}
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const bool use_big_pages = alloc->second.big_pages && big_page;
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gmmu->Map(params.offset, cpu_address, size, use_big_pages);
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gmmu->Map(params.offset, cpu_address, size, static_cast<Tegra::PTEKind>(params.kind),
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use_big_pages);
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auto mapping{std::make_shared<Mapping>(cpu_address, params.offset, size, true,
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use_big_pages, alloc->second.sparse)};
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@ -409,7 +412,8 @@ NvResult nvhost_as_gpu::MapBufferEx(const std::vector<u8>& input, std::vector<u8
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return NvResult::InsufficientMemory;
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}
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gmmu->Map(params.offset, cpu_address, Common::AlignUp(size, page_size), big_page);
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gmmu->Map(params.offset, cpu_address, Common::AlignUp(size, page_size),
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static_cast<Tegra::PTEKind>(params.kind), big_page);
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auto mapping{
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std::make_shared<Mapping>(cpu_address, params.offset, size, false, big_page, false)};
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@ -82,6 +82,7 @@ add_library(video_core STATIC
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gpu_thread.h
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memory_manager.cpp
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memory_manager.h
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pte_kind.h
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query_cache.h
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rasterizer_accelerated.cpp
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rasterizer_accelerated.h
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@ -56,68 +56,87 @@ void MaxwellDMA::Launch() {
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ASSERT(launch.interrupt_type == LaunchDMA::InterruptType::NONE);
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ASSERT(launch.data_transfer_type == LaunchDMA::DataTransferType::NON_PIPELINED);
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const bool is_src_pitch = launch.src_memory_layout == LaunchDMA::MemoryLayout::PITCH;
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const bool is_dst_pitch = launch.dst_memory_layout == LaunchDMA::MemoryLayout::PITCH;
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if (launch.multi_line_enable) {
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const bool is_src_pitch = launch.src_memory_layout == LaunchDMA::MemoryLayout::PITCH;
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const bool is_dst_pitch = launch.dst_memory_layout == LaunchDMA::MemoryLayout::PITCH;
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if (!is_src_pitch && !is_dst_pitch) {
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// If both the source and the destination are in block layout, assert.
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UNIMPLEMENTED_MSG("Tiled->Tiled DMA transfers are not yet implemented");
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return;
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}
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if (!is_src_pitch && !is_dst_pitch) {
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// If both the source and the destination are in block layout, assert.
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UNIMPLEMENTED_MSG("Tiled->Tiled DMA transfers are not yet implemented");
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return;
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}
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if (is_src_pitch && is_dst_pitch) {
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CopyPitchToPitch();
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} else {
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ASSERT(launch.multi_line_enable == 1);
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if (!is_src_pitch && is_dst_pitch) {
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CopyBlockLinearToPitch();
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if (is_src_pitch && is_dst_pitch) {
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for (u32 line = 0; line < regs.line_count; ++line) {
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const GPUVAddr source_line =
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regs.offset_in + static_cast<size_t>(line) * regs.pitch_in;
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const GPUVAddr dest_line =
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regs.offset_out + static_cast<size_t>(line) * regs.pitch_out;
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memory_manager.CopyBlock(dest_line, source_line, regs.line_length_in);
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}
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} else {
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CopyPitchToBlockLinear();
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if (!is_src_pitch && is_dst_pitch) {
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CopyBlockLinearToPitch();
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} else {
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CopyPitchToBlockLinear();
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}
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}
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} else {
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// TODO: allow multisized components.
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auto& accelerate = rasterizer->AccessAccelerateDMA();
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const bool is_const_a_dst = regs.remap_const.dst_x == RemapConst::Swizzle::CONST_A;
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if (regs.launch_dma.remap_enable != 0 && is_const_a_dst) {
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ASSERT(regs.remap_const.component_size_minus_one == 3);
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accelerate.BufferClear(regs.offset_out, regs.line_length_in, regs.remap_consta_value);
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std::vector<u32> tmp_buffer(regs.line_length_in, regs.remap_consta_value);
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memory_manager.WriteBlockUnsafe(regs.offset_out,
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reinterpret_cast<u8*>(tmp_buffer.data()),
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regs.line_length_in * sizeof(u32));
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} else {
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auto convert_linear_2_blocklinear_addr = [](u64 address) {
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return (address & ~0x1f0ULL) | ((address & 0x40) >> 2) | ((address & 0x10) << 1) |
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((address & 0x180) >> 1) | ((address & 0x20) << 3);
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};
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auto src_kind = memory_manager.GetPageKind(regs.offset_in);
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auto dst_kind = memory_manager.GetPageKind(regs.offset_out);
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const bool is_src_pitch = IsPitchKind(static_cast<PTEKind>(src_kind));
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const bool is_dst_pitch = IsPitchKind(static_cast<PTEKind>(dst_kind));
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if (!is_src_pitch && is_dst_pitch) {
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std::vector<u8> tmp_buffer(regs.line_length_in);
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std::vector<u8> dst_buffer(regs.line_length_in);
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memory_manager.ReadBlockUnsafe(regs.offset_in, tmp_buffer.data(),
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regs.line_length_in);
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for (u32 offset = 0; offset < regs.line_length_in; ++offset) {
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dst_buffer[offset] =
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tmp_buffer[convert_linear_2_blocklinear_addr(regs.offset_in + offset) -
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regs.offset_in];
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}
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memory_manager.WriteBlock(regs.offset_out, dst_buffer.data(), regs.line_length_in);
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} else if (is_src_pitch && !is_dst_pitch) {
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std::vector<u8> tmp_buffer(regs.line_length_in);
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std::vector<u8> dst_buffer(regs.line_length_in);
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memory_manager.ReadBlockUnsafe(regs.offset_in, tmp_buffer.data(),
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regs.line_length_in);
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for (u32 offset = 0; offset < regs.line_length_in; ++offset) {
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dst_buffer[convert_linear_2_blocklinear_addr(regs.offset_out + offset) -
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regs.offset_out] = tmp_buffer[offset];
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}
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memory_manager.WriteBlock(regs.offset_out, dst_buffer.data(), regs.line_length_in);
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} else {
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if (!accelerate.BufferCopy(regs.offset_in, regs.offset_out, regs.line_length_in)) {
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std::vector<u8> tmp_buffer(regs.line_length_in);
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memory_manager.ReadBlockUnsafe(regs.offset_in, tmp_buffer.data(),
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regs.line_length_in);
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memory_manager.WriteBlock(regs.offset_out, tmp_buffer.data(),
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regs.line_length_in);
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}
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}
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}
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}
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ReleaseSemaphore();
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}
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void MaxwellDMA::CopyPitchToPitch() {
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// When `multi_line_enable` bit is enabled we copy a 2D image of dimensions
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// (line_length_in, line_count).
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// Otherwise the copy is performed as if we were copying a 1D buffer of length line_length_in.
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const bool remap_enabled = regs.launch_dma.remap_enable != 0;
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if (regs.launch_dma.multi_line_enable) {
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UNIMPLEMENTED_IF(remap_enabled);
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// Perform a line-by-line copy.
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// We're going to take a subrect of size (line_length_in, line_count) from the source
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// rectangle. There is no need to manually flush/invalidate the regions because CopyBlock
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// does that for us.
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for (u32 line = 0; line < regs.line_count; ++line) {
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const GPUVAddr source_line = regs.offset_in + static_cast<size_t>(line) * regs.pitch_in;
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const GPUVAddr dest_line = regs.offset_out + static_cast<size_t>(line) * regs.pitch_out;
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memory_manager.CopyBlock(dest_line, source_line, regs.line_length_in);
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}
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return;
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}
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// TODO: allow multisized components.
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auto& accelerate = rasterizer->AccessAccelerateDMA();
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const bool is_const_a_dst = regs.remap_const.dst_x == RemapConst::Swizzle::CONST_A;
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const bool is_buffer_clear = remap_enabled && is_const_a_dst;
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if (is_buffer_clear) {
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ASSERT(regs.remap_const.component_size_minus_one == 3);
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accelerate.BufferClear(regs.offset_out, regs.line_length_in, regs.remap_consta_value);
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std::vector<u32> tmp_buffer(regs.line_length_in, regs.remap_consta_value);
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memory_manager.WriteBlockUnsafe(regs.offset_out, reinterpret_cast<u8*>(tmp_buffer.data()),
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regs.line_length_in * sizeof(u32));
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return;
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}
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UNIMPLEMENTED_IF(remap_enabled);
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if (!accelerate.BufferCopy(regs.offset_in, regs.offset_out, regs.line_length_in)) {
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std::vector<u8> tmp_buffer(regs.line_length_in);
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memory_manager.ReadBlockUnsafe(regs.offset_in, tmp_buffer.data(), regs.line_length_in);
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memory_manager.WriteBlock(regs.offset_out, tmp_buffer.data(), regs.line_length_in);
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}
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}
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void MaxwellDMA::CopyBlockLinearToPitch() {
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UNIMPLEMENTED_IF(regs.src_params.block_size.width != 0);
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UNIMPLEMENTED_IF(regs.src_params.layer != 0);
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@ -219,8 +219,6 @@ private:
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/// registers.
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void Launch();
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void CopyPitchToPitch();
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void CopyBlockLinearToPitch();
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void CopyPitchToBlockLinear();
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@ -41,7 +41,11 @@ MemoryManager::MemoryManager(Core::System& system_, u64 address_space_bits_, u64
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big_entries.resize(big_page_table_size / 32, 0);
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big_page_table_cpu.resize(big_page_table_size);
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big_page_continous.resize(big_page_table_size / continous_bits, 0);
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std::array<PTEKind, 32> kind_valus;
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kind_valus.fill(PTEKind::INVALID);
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big_kinds.resize(big_page_table_size / 32, kind_valus);
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entries.resize(page_table_size / 32, 0);
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kinds.resize(big_page_table_size / 32, kind_valus);
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}
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MemoryManager::~MemoryManager() = default;
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@ -78,6 +82,41 @@ void MemoryManager::SetEntry(size_t position, MemoryManager::EntryType entry) {
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}
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}
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PTEKind MemoryManager::GetPageKind(GPUVAddr gpu_addr) const {
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auto entry = GetEntry<true>(gpu_addr);
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if (entry == EntryType::Mapped || entry == EntryType::Reserved) [[likely]] {
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return GetKind<true>(gpu_addr);
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} else {
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return GetKind<false>(gpu_addr);
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}
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}
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template <bool is_big_page>
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PTEKind MemoryManager::GetKind(size_t position) const {
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if constexpr (is_big_page) {
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position = position >> big_page_bits;
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const size_t sub_index = position % 32;
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return big_kinds[position / 32][sub_index];
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} else {
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position = position >> page_bits;
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const size_t sub_index = position % 32;
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return kinds[position / 32][sub_index];
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}
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}
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template <bool is_big_page>
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void MemoryManager::SetKind(size_t position, PTEKind kind) {
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if constexpr (is_big_page) {
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position = position >> big_page_bits;
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const size_t sub_index = position % 32;
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big_kinds[position / 32][sub_index] = kind;
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} else {
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position = position >> page_bits;
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const size_t sub_index = position % 32;
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kinds[position / 32][sub_index] = kind;
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}
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}
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inline bool MemoryManager::IsBigPageContinous(size_t big_page_index) const {
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const u64 entry_mask = big_page_continous[big_page_index / continous_bits];
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const size_t sub_index = big_page_index % continous_bits;
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@ -92,8 +131,8 @@ inline void MemoryManager::SetBigPageContinous(size_t big_page_index, bool value
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}
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template <MemoryManager::EntryType entry_type>
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GPUVAddr MemoryManager::PageTableOp(GPUVAddr gpu_addr, [[maybe_unused]] VAddr cpu_addr,
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size_t size) {
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GPUVAddr MemoryManager::PageTableOp(GPUVAddr gpu_addr, [[maybe_unused]] VAddr cpu_addr, size_t size,
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PTEKind kind) {
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u64 remaining_size{size};
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if constexpr (entry_type == EntryType::Mapped) {
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page_table.ReserveRange(gpu_addr, size);
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@ -102,6 +141,7 @@ GPUVAddr MemoryManager::PageTableOp(GPUVAddr gpu_addr, [[maybe_unused]] VAddr cp
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const GPUVAddr current_gpu_addr = gpu_addr + offset;
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[[maybe_unused]] const auto current_entry_type = GetEntry<false>(current_gpu_addr);
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SetEntry<false>(current_gpu_addr, entry_type);
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SetKind<false>(current_gpu_addr, kind);
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if (current_entry_type != entry_type) {
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rasterizer->ModifyGPUMemory(unique_identifier, gpu_addr, page_size);
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}
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@ -118,12 +158,13 @@ GPUVAddr MemoryManager::PageTableOp(GPUVAddr gpu_addr, [[maybe_unused]] VAddr cp
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template <MemoryManager::EntryType entry_type>
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GPUVAddr MemoryManager::BigPageTableOp(GPUVAddr gpu_addr, [[maybe_unused]] VAddr cpu_addr,
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size_t size) {
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size_t size, PTEKind kind) {
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u64 remaining_size{size};
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for (u64 offset{}; offset < size; offset += big_page_size) {
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const GPUVAddr current_gpu_addr = gpu_addr + offset;
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[[maybe_unused]] const auto current_entry_type = GetEntry<true>(current_gpu_addr);
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SetEntry<true>(current_gpu_addr, entry_type);
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SetKind<true>(current_gpu_addr, kind);
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if (current_entry_type != entry_type) {
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rasterizer->ModifyGPUMemory(unique_identifier, gpu_addr, big_page_size);
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}
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@ -159,19 +200,19 @@ void MemoryManager::BindRasterizer(VideoCore::RasterizerInterface* rasterizer_)
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rasterizer = rasterizer_;
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}
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GPUVAddr MemoryManager::Map(GPUVAddr gpu_addr, VAddr cpu_addr, std::size_t size,
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GPUVAddr MemoryManager::Map(GPUVAddr gpu_addr, VAddr cpu_addr, std::size_t size, PTEKind kind,
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bool is_big_pages) {
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if (is_big_pages) [[likely]] {
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return BigPageTableOp<EntryType::Mapped>(gpu_addr, cpu_addr, size);
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return BigPageTableOp<EntryType::Mapped>(gpu_addr, cpu_addr, size, kind);
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}
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return PageTableOp<EntryType::Mapped>(gpu_addr, cpu_addr, size);
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return PageTableOp<EntryType::Mapped>(gpu_addr, cpu_addr, size, kind);
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}
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GPUVAddr MemoryManager::MapSparse(GPUVAddr gpu_addr, std::size_t size, bool is_big_pages) {
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if (is_big_pages) [[likely]] {
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return BigPageTableOp<EntryType::Reserved>(gpu_addr, 0, size);
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return BigPageTableOp<EntryType::Reserved>(gpu_addr, 0, size, PTEKind::INVALID);
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}
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return PageTableOp<EntryType::Reserved>(gpu_addr, 0, size);
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return PageTableOp<EntryType::Reserved>(gpu_addr, 0, size, PTEKind::INVALID);
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}
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void MemoryManager::Unmap(GPUVAddr gpu_addr, std::size_t size) {
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@ -188,8 +229,8 @@ void MemoryManager::Unmap(GPUVAddr gpu_addr, std::size_t size) {
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rasterizer->UnmapMemory(*cpu_addr, map_size);
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}
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BigPageTableOp<EntryType::Free>(gpu_addr, 0, size);
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PageTableOp<EntryType::Free>(gpu_addr, 0, size);
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BigPageTableOp<EntryType::Free>(gpu_addr, 0, size, PTEKind::INVALID);
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PageTableOp<EntryType::Free>(gpu_addr, 0, size, PTEKind::INVALID);
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}
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std::optional<VAddr> MemoryManager::GpuToCpuAddress(GPUVAddr gpu_addr) const {
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@ -11,6 +11,7 @@
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#include "common/common_types.h"
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#include "common/multi_level_page_table.h"
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#include "common/virtual_buffer.h"
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#include "video_core/pte_kind.h"
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namespace VideoCore {
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class RasterizerInterface;
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@ -98,7 +99,8 @@ public:
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std::vector<std::pair<GPUVAddr, std::size_t>> GetSubmappedRange(GPUVAddr gpu_addr,
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std::size_t size) const;
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GPUVAddr Map(GPUVAddr gpu_addr, VAddr cpu_addr, std::size_t size, bool is_big_pages = true);
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GPUVAddr Map(GPUVAddr gpu_addr, VAddr cpu_addr, std::size_t size,
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PTEKind kind = PTEKind::INVALID, bool is_big_pages = true);
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GPUVAddr MapSparse(GPUVAddr gpu_addr, std::size_t size, bool is_big_pages = true);
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void Unmap(GPUVAddr gpu_addr, std::size_t size);
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@ -114,6 +116,8 @@ public:
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return gpu_addr < address_space_size;
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}
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PTEKind GetPageKind(GPUVAddr gpu_addr) const;
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private:
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template <bool is_big_pages, typename FuncMapped, typename FuncReserved, typename FuncUnmapped>
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inline void MemoryOperation(GPUVAddr gpu_src_addr, std::size_t size, FuncMapped&& func_mapped,
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@ -166,10 +170,12 @@ private:
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std::vector<u64> big_entries;
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template <EntryType entry_type>
|
||||
GPUVAddr PageTableOp(GPUVAddr gpu_addr, [[maybe_unused]] VAddr cpu_addr, size_t size);
|
||||
GPUVAddr PageTableOp(GPUVAddr gpu_addr, [[maybe_unused]] VAddr cpu_addr, size_t size,
|
||||
PTEKind kind);
|
||||
|
||||
template <EntryType entry_type>
|
||||
GPUVAddr BigPageTableOp(GPUVAddr gpu_addr, [[maybe_unused]] VAddr cpu_addr, size_t size);
|
||||
GPUVAddr BigPageTableOp(GPUVAddr gpu_addr, [[maybe_unused]] VAddr cpu_addr, size_t size,
|
||||
PTEKind kind);
|
||||
|
||||
template <bool is_big_page>
|
||||
inline EntryType GetEntry(size_t position) const;
|
||||
|
|
@ -177,6 +183,15 @@ private:
|
|||
template <bool is_big_page>
|
||||
inline void SetEntry(size_t position, EntryType entry);
|
||||
|
||||
std::vector<std::array<PTEKind, 32>> kinds;
|
||||
std::vector<std::array<PTEKind, 32>> big_kinds;
|
||||
|
||||
template <bool is_big_page>
|
||||
inline PTEKind GetKind(size_t position) const;
|
||||
|
||||
template <bool is_big_page>
|
||||
inline void SetKind(size_t position, PTEKind kind);
|
||||
|
||||
Common::MultiLevelPageTable<u32> page_table;
|
||||
Common::VirtualBuffer<u32> big_page_table_cpu;
|
||||
|
||||
|
|
|
|||
264
src/video_core/pte_kind.h
Normal file
264
src/video_core/pte_kind.h
Normal file
|
|
@ -0,0 +1,264 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2022 yuzu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "common/common_types.h"
|
||||
|
||||
namespace Tegra {
|
||||
|
||||
// https://github.com/NVIDIA/open-gpu-doc/blob/master/manuals/volta/gv100/dev_mmu.ref.txt
|
||||
enum class PTEKind : u8 {
|
||||
INVALID = 0xff,
|
||||
PITCH = 0x00,
|
||||
Z16 = 0x01,
|
||||
Z16_2C = 0x02,
|
||||
Z16_MS2_2C = 0x03,
|
||||
Z16_MS4_2C = 0x04,
|
||||
Z16_MS8_2C = 0x05,
|
||||
Z16_MS16_2C = 0x06,
|
||||
Z16_2Z = 0x07,
|
||||
Z16_MS2_2Z = 0x08,
|
||||
Z16_MS4_2Z = 0x09,
|
||||
Z16_MS8_2Z = 0x0a,
|
||||
Z16_MS16_2Z = 0x0b,
|
||||
Z16_2CZ = 0x36,
|
||||
Z16_MS2_2CZ = 0x37,
|
||||
Z16_MS4_2CZ = 0x38,
|
||||
Z16_MS8_2CZ = 0x39,
|
||||
Z16_MS16_2CZ = 0x5f,
|
||||
Z16_4CZ = 0x0c,
|
||||
Z16_MS2_4CZ = 0x0d,
|
||||
Z16_MS4_4CZ = 0x0e,
|
||||
Z16_MS8_4CZ = 0x0f,
|
||||
Z16_MS16_4CZ = 0x10,
|
||||
S8Z24 = 0x11,
|
||||
S8Z24_1Z = 0x12,
|
||||
S8Z24_MS2_1Z = 0x13,
|
||||
S8Z24_MS4_1Z = 0x14,
|
||||
S8Z24_MS8_1Z = 0x15,
|
||||
S8Z24_MS16_1Z = 0x16,
|
||||
S8Z24_2CZ = 0x17,
|
||||
S8Z24_MS2_2CZ = 0x18,
|
||||
S8Z24_MS4_2CZ = 0x19,
|
||||
S8Z24_MS8_2CZ = 0x1a,
|
||||
S8Z24_MS16_2CZ = 0x1b,
|
||||
S8Z24_2CS = 0x1c,
|
||||
S8Z24_MS2_2CS = 0x1d,
|
||||
S8Z24_MS4_2CS = 0x1e,
|
||||
S8Z24_MS8_2CS = 0x1f,
|
||||
S8Z24_MS16_2CS = 0x20,
|
||||
S8Z24_4CSZV = 0x21,
|
||||
S8Z24_MS2_4CSZV = 0x22,
|
||||
S8Z24_MS4_4CSZV = 0x23,
|
||||
S8Z24_MS8_4CSZV = 0x24,
|
||||
S8Z24_MS16_4CSZV = 0x25,
|
||||
V8Z24_MS4_VC12 = 0x26,
|
||||
V8Z24_MS4_VC4 = 0x27,
|
||||
V8Z24_MS8_VC8 = 0x28,
|
||||
V8Z24_MS8_VC24 = 0x29,
|
||||
V8Z24_MS4_VC12_1ZV = 0x2e,
|
||||
V8Z24_MS4_VC4_1ZV = 0x2f,
|
||||
V8Z24_MS8_VC8_1ZV = 0x30,
|
||||
V8Z24_MS8_VC24_1ZV = 0x31,
|
||||
V8Z24_MS4_VC12_2CS = 0x32,
|
||||
V8Z24_MS4_VC4_2CS = 0x33,
|
||||
V8Z24_MS8_VC8_2CS = 0x34,
|
||||
V8Z24_MS8_VC24_2CS = 0x35,
|
||||
V8Z24_MS4_VC12_2CZV = 0x3a,
|
||||
V8Z24_MS4_VC4_2CZV = 0x3b,
|
||||
V8Z24_MS8_VC8_2CZV = 0x3c,
|
||||
V8Z24_MS8_VC24_2CZV = 0x3d,
|
||||
V8Z24_MS4_VC12_2ZV = 0x3e,
|
||||
V8Z24_MS4_VC4_2ZV = 0x3f,
|
||||
V8Z24_MS8_VC8_2ZV = 0x40,
|
||||
V8Z24_MS8_VC24_2ZV = 0x41,
|
||||
V8Z24_MS4_VC12_4CSZV = 0x42,
|
||||
V8Z24_MS4_VC4_4CSZV = 0x43,
|
||||
V8Z24_MS8_VC8_4CSZV = 0x44,
|
||||
V8Z24_MS8_VC24_4CSZV = 0x45,
|
||||
Z24S8 = 0x46,
|
||||
Z24S8_1Z = 0x47,
|
||||
Z24S8_MS2_1Z = 0x48,
|
||||
Z24S8_MS4_1Z = 0x49,
|
||||
Z24S8_MS8_1Z = 0x4a,
|
||||
Z24S8_MS16_1Z = 0x4b,
|
||||
Z24S8_2CS = 0x4c,
|
||||
Z24S8_MS2_2CS = 0x4d,
|
||||
Z24S8_MS4_2CS = 0x4e,
|
||||
Z24S8_MS8_2CS = 0x4f,
|
||||
Z24S8_MS16_2CS = 0x50,
|
||||
Z24S8_2CZ = 0x51,
|
||||
Z24S8_MS2_2CZ = 0x52,
|
||||
Z24S8_MS4_2CZ = 0x53,
|
||||
Z24S8_MS8_2CZ = 0x54,
|
||||
Z24S8_MS16_2CZ = 0x55,
|
||||
Z24S8_4CSZV = 0x56,
|
||||
Z24S8_MS2_4CSZV = 0x57,
|
||||
Z24S8_MS4_4CSZV = 0x58,
|
||||
Z24S8_MS8_4CSZV = 0x59,
|
||||
Z24S8_MS16_4CSZV = 0x5a,
|
||||
Z24V8_MS4_VC12 = 0x5b,
|
||||
Z24V8_MS4_VC4 = 0x5c,
|
||||
Z24V8_MS8_VC8 = 0x5d,
|
||||
Z24V8_MS8_VC24 = 0x5e,
|
||||
YUV_B8C1_2Y = 0x60,
|
||||
YUV_B8C2_2Y = 0x61,
|
||||
YUV_B10C1_2Y = 0x62,
|
||||
YUV_B10C2_2Y = 0x6b,
|
||||
YUV_B12C1_2Y = 0x6c,
|
||||
YUV_B12C2_2Y = 0x6d,
|
||||
Z24V8_MS4_VC12_1ZV = 0x63,
|
||||
Z24V8_MS4_VC4_1ZV = 0x64,
|
||||
Z24V8_MS8_VC8_1ZV = 0x65,
|
||||
Z24V8_MS8_VC24_1ZV = 0x66,
|
||||
Z24V8_MS4_VC12_2CS = 0x67,
|
||||
Z24V8_MS4_VC4_2CS = 0x68,
|
||||
Z24V8_MS8_VC8_2CS = 0x69,
|
||||
Z24V8_MS8_VC24_2CS = 0x6a,
|
||||
Z24V8_MS4_VC12_2CZV = 0x6f,
|
||||
Z24V8_MS4_VC4_2CZV = 0x70,
|
||||
Z24V8_MS8_VC8_2CZV = 0x71,
|
||||
Z24V8_MS8_VC24_2CZV = 0x72,
|
||||
Z24V8_MS4_VC12_2ZV = 0x73,
|
||||
Z24V8_MS4_VC4_2ZV = 0x74,
|
||||
Z24V8_MS8_VC8_2ZV = 0x75,
|
||||
Z24V8_MS8_VC24_2ZV = 0x76,
|
||||
Z24V8_MS4_VC12_4CSZV = 0x77,
|
||||
Z24V8_MS4_VC4_4CSZV = 0x78,
|
||||
Z24V8_MS8_VC8_4CSZV = 0x79,
|
||||
Z24V8_MS8_VC24_4CSZV = 0x7a,
|
||||
ZF32 = 0x7b,
|
||||
ZF32_1Z = 0x7c,
|
||||
ZF32_MS2_1Z = 0x7d,
|
||||
ZF32_MS4_1Z = 0x7e,
|
||||
ZF32_MS8_1Z = 0x7f,
|
||||
ZF32_MS16_1Z = 0x80,
|
||||
ZF32_2CS = 0x81,
|
||||
ZF32_MS2_2CS = 0x82,
|
||||
ZF32_MS4_2CS = 0x83,
|
||||
ZF32_MS8_2CS = 0x84,
|
||||
ZF32_MS16_2CS = 0x85,
|
||||
ZF32_2CZ = 0x86,
|
||||
ZF32_MS2_2CZ = 0x87,
|
||||
ZF32_MS4_2CZ = 0x88,
|
||||
ZF32_MS8_2CZ = 0x89,
|
||||
ZF32_MS16_2CZ = 0x8a,
|
||||
X8Z24_X16V8S8_MS4_VC12 = 0x8b,
|
||||
X8Z24_X16V8S8_MS4_VC4 = 0x8c,
|
||||
X8Z24_X16V8S8_MS8_VC8 = 0x8d,
|
||||
X8Z24_X16V8S8_MS8_VC24 = 0x8e,
|
||||
X8Z24_X16V8S8_MS4_VC12_1CS = 0x8f,
|
||||
X8Z24_X16V8S8_MS4_VC4_1CS = 0x90,
|
||||
X8Z24_X16V8S8_MS8_VC8_1CS = 0x91,
|
||||
X8Z24_X16V8S8_MS8_VC24_1CS = 0x92,
|
||||
X8Z24_X16V8S8_MS4_VC12_1ZV = 0x97,
|
||||
X8Z24_X16V8S8_MS4_VC4_1ZV = 0x98,
|
||||
X8Z24_X16V8S8_MS8_VC8_1ZV = 0x99,
|
||||
X8Z24_X16V8S8_MS8_VC24_1ZV = 0x9a,
|
||||
X8Z24_X16V8S8_MS4_VC12_1CZV = 0x9b,
|
||||
X8Z24_X16V8S8_MS4_VC4_1CZV = 0x9c,
|
||||
X8Z24_X16V8S8_MS8_VC8_1CZV = 0x9d,
|
||||
X8Z24_X16V8S8_MS8_VC24_1CZV = 0x9e,
|
||||
X8Z24_X16V8S8_MS4_VC12_2CS = 0x9f,
|
||||
X8Z24_X16V8S8_MS4_VC4_2CS = 0xa0,
|
||||
X8Z24_X16V8S8_MS8_VC8_2CS = 0xa1,
|
||||
X8Z24_X16V8S8_MS8_VC24_2CS = 0xa2,
|
||||
X8Z24_X16V8S8_MS4_VC12_2CSZV = 0xa3,
|
||||
X8Z24_X16V8S8_MS4_VC4_2CSZV = 0xa4,
|
||||
X8Z24_X16V8S8_MS8_VC8_2CSZV = 0xa5,
|
||||
X8Z24_X16V8S8_MS8_VC24_2CSZV = 0xa6,
|
||||
ZF32_X16V8S8_MS4_VC12 = 0xa7,
|
||||
ZF32_X16V8S8_MS4_VC4 = 0xa8,
|
||||
ZF32_X16V8S8_MS8_VC8 = 0xa9,
|
||||
ZF32_X16V8S8_MS8_VC24 = 0xaa,
|
||||
ZF32_X16V8S8_MS4_VC12_1CS = 0xab,
|
||||
ZF32_X16V8S8_MS4_VC4_1CS = 0xac,
|
||||
ZF32_X16V8S8_MS8_VC8_1CS = 0xad,
|
||||
ZF32_X16V8S8_MS8_VC24_1CS = 0xae,
|
||||
ZF32_X16V8S8_MS4_VC12_1ZV = 0xb3,
|
||||
ZF32_X16V8S8_MS4_VC4_1ZV = 0xb4,
|
||||
ZF32_X16V8S8_MS8_VC8_1ZV = 0xb5,
|
||||
ZF32_X16V8S8_MS8_VC24_1ZV = 0xb6,
|
||||
ZF32_X16V8S8_MS4_VC12_1CZV = 0xb7,
|
||||
ZF32_X16V8S8_MS4_VC4_1CZV = 0xb8,
|
||||
ZF32_X16V8S8_MS8_VC8_1CZV = 0xb9,
|
||||
ZF32_X16V8S8_MS8_VC24_1CZV = 0xba,
|
||||
ZF32_X16V8S8_MS4_VC12_2CS = 0xbb,
|
||||
ZF32_X16V8S8_MS4_VC4_2CS = 0xbc,
|
||||
ZF32_X16V8S8_MS8_VC8_2CS = 0xbd,
|
||||
ZF32_X16V8S8_MS8_VC24_2CS = 0xbe,
|
||||
ZF32_X16V8S8_MS4_VC12_2CSZV = 0xbf,
|
||||
ZF32_X16V8S8_MS4_VC4_2CSZV = 0xc0,
|
||||
ZF32_X16V8S8_MS8_VC8_2CSZV = 0xc1,
|
||||
ZF32_X16V8S8_MS8_VC24_2CSZV = 0xc2,
|
||||
ZF32_X24S8 = 0xc3,
|
||||
ZF32_X24S8_1CS = 0xc4,
|
||||
ZF32_X24S8_MS2_1CS = 0xc5,
|
||||
ZF32_X24S8_MS4_1CS = 0xc6,
|
||||
ZF32_X24S8_MS8_1CS = 0xc7,
|
||||
ZF32_X24S8_MS16_1CS = 0xc8,
|
||||
ZF32_X24S8_2CSZV = 0xce,
|
||||
ZF32_X24S8_MS2_2CSZV = 0xcf,
|
||||
ZF32_X24S8_MS4_2CSZV = 0xd0,
|
||||
ZF32_X24S8_MS8_2CSZV = 0xd1,
|
||||
ZF32_X24S8_MS16_2CSZV = 0xd2,
|
||||
ZF32_X24S8_2CS = 0xd3,
|
||||
ZF32_X24S8_MS2_2CS = 0xd4,
|
||||
ZF32_X24S8_MS4_2CS = 0xd5,
|
||||
ZF32_X24S8_MS8_2CS = 0xd6,
|
||||
ZF32_X24S8_MS16_2CS = 0xd7,
|
||||
S8 = 0x2a,
|
||||
S8_2S = 0x2b,
|
||||
GENERIC_16BX2 = 0xfe,
|
||||
C32_2C = 0xd8,
|
||||
C32_2CBR = 0xd9,
|
||||
C32_2CBA = 0xda,
|
||||
C32_2CRA = 0xdb,
|
||||
C32_2BRA = 0xdc,
|
||||
C32_MS2_2C = 0xdd,
|
||||
C32_MS2_2CBR = 0xde,
|
||||
C32_MS2_4CBRA = 0xcc,
|
||||
C32_MS4_2C = 0xdf,
|
||||
C32_MS4_2CBR = 0xe0,
|
||||
C32_MS4_2CBA = 0xe1,
|
||||
C32_MS4_2CRA = 0xe2,
|
||||
C32_MS4_2BRA = 0xe3,
|
||||
C32_MS4_4CBRA = 0x2c,
|
||||
C32_MS8_MS16_2C = 0xe4,
|
||||
C32_MS8_MS16_2CRA = 0xe5,
|
||||
C64_2C = 0xe6,
|
||||
C64_2CBR = 0xe7,
|
||||
C64_2CBA = 0xe8,
|
||||
C64_2CRA = 0xe9,
|
||||
C64_2BRA = 0xea,
|
||||
C64_MS2_2C = 0xeb,
|
||||
C64_MS2_2CBR = 0xec,
|
||||
C64_MS2_4CBRA = 0xcd,
|
||||
C64_MS4_2C = 0xed,
|
||||
C64_MS4_2CBR = 0xee,
|
||||
C64_MS4_2CBA = 0xef,
|
||||
C64_MS4_2CRA = 0xf0,
|
||||
C64_MS4_2BRA = 0xf1,
|
||||
C64_MS4_4CBRA = 0x2d,
|
||||
C64_MS8_MS16_2C = 0xf2,
|
||||
C64_MS8_MS16_2CRA = 0xf3,
|
||||
C128_2C = 0xf4,
|
||||
C128_2CR = 0xf5,
|
||||
C128_MS2_2C = 0xf6,
|
||||
C128_MS2_2CR = 0xf7,
|
||||
C128_MS4_2C = 0xf8,
|
||||
C128_MS4_2CR = 0xf9,
|
||||
C128_MS8_MS16_2C = 0xfa,
|
||||
C128_MS8_MS16_2CR = 0xfb,
|
||||
X8C24 = 0xfc,
|
||||
PITCH_NO_SWIZZLE = 0xfd,
|
||||
SMSKED_MESSAGE = 0xca,
|
||||
SMHOST_MESSAGE = 0xcb,
|
||||
};
|
||||
|
||||
constexpr bool IsPitchKind(PTEKind kind) {
|
||||
return kind == PTEKind::PITCH || kind == PTEKind::PITCH_NO_SWIZZLE;
|
||||
}
|
||||
|
||||
} // namespace Tegra
|
||||
Loading…
Reference in a new issue