mirror of
https://github.com/yuzu-mirror/yuzu.git
synced 2024-09-07 09:49:08 +01:00
Revamp Kepler Memory to use a subegine to manage uploads
This commit is contained in:
parent
b5889cbd6f
commit
a91d3fc639
6 changed files with 134 additions and 93 deletions
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@ -3,6 +3,8 @@ add_library(video_core STATIC
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dma_pusher.h
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dma_pusher.h
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debug_utils/debug_utils.cpp
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debug_utils/debug_utils.cpp
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debug_utils/debug_utils.h
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debug_utils/debug_utils.h
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engines/engine_upload.cpp
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engines/engine_upload.h
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engines/fermi_2d.cpp
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engines/fermi_2d.cpp
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engines/fermi_2d.h
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engines/fermi_2d.h
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engines/kepler_compute.cpp
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engines/kepler_compute.cpp
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44
src/video_core/engines/engine_upload.cpp
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44
src/video_core/engines/engine_upload.cpp
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@ -0,0 +1,44 @@
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// Copyright 2019 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "video_core/engines/engine_upload.h"
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#include "video_core/memory_manager.h"
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#include "video_core/textures/decoders.h"
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namespace Tegra::Engines::Upload {
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void State::ProcessExec(const bool is_linear) {
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write_offset = 0;
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copy_size = regs.line_length_in * regs.line_count;
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inner_buffer.resize(copy_size);
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linear = is_linear;
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}
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void State::ProcessData(const u32 data, const bool is_last_call) {
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const u32 sub_copy_size = std::min(4U, copy_size - write_offset);
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std::memcpy(&inner_buffer[write_offset], &data, sub_copy_size);
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write_offset += sub_copy_size;
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if (is_last_call) {
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const GPUVAddr address{regs.dest.Address()};
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if (linear) {
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memory_manager.WriteBlock(address, inner_buffer.data(), copy_size);
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} else {
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UNIMPLEMENTED_IF(regs.dest.z != 0);
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UNIMPLEMENTED_IF(regs.dest.depth != 1);
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UNIMPLEMENTED_IF(regs.dest.BlockWidth() != 1);
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UNIMPLEMENTED_IF(regs.dest.BlockDepth() != 1);
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const std::size_t dst_size = Tegra::Texture::CalculateSize(
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true, 1, regs.dest.width, regs.dest.height, 1, regs.dest.BlockHeight(), 1);
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std::vector<u8> tmp_buffer(dst_size);
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memory_manager.ReadBlock(address, tmp_buffer.data(), dst_size);
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Tegra::Texture::SwizzleKepler(regs.dest.width, regs.dest.height, regs.dest.x,
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regs.dest.y, regs.dest.BlockHeight(), copy_size,
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inner_buffer.data(), tmp_buffer.data());
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memory_manager.WriteBlock(address, tmp_buffer.data(), dst_size);
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}
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}
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}
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} // namespace Tegra::Engines::Upload
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74
src/video_core/engines/engine_upload.h
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74
src/video_core/engines/engine_upload.h
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@ -0,0 +1,74 @@
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// Copyright 2019 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <cstddef>
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#include <vector>
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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namespace Tegra {
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class MemoryManager;
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}
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namespace Tegra::Engines::Upload {
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struct Data {
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u32 line_length_in;
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u32 line_count;
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struct {
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u32 address_high;
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u32 address_low;
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u32 pitch;
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union {
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BitField<0, 4, u32> block_width;
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BitField<4, 4, u32> block_height;
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BitField<8, 4, u32> block_depth;
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};
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u32 width;
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u32 height;
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u32 depth;
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u32 z;
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u32 x;
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u32 y;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) | address_low);
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}
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u32 BlockWidth() const {
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return 1U << block_width.Value();
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}
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u32 BlockHeight() const {
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return 1U << block_height.Value();
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}
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u32 BlockDepth() const {
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return 1U << block_depth.Value();
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}
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} dest;
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};
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class State {
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public:
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State(MemoryManager& memory_manager, Data& regs) : memory_manager(memory_manager), regs(regs) {}
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~State() = default;
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void ProcessExec(const bool is_linear);
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void ProcessData(const u32 data, const bool is_last_call);
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private:
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u32 write_offset = 0;
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u32 copy_size = 0;
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std::vector<u8> inner_buffer;
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bool linear;
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Data& regs;
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MemoryManager& memory_manager;
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};
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} // namespace Tegra::Engines::Upload
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@ -14,9 +14,8 @@
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namespace Tegra::Engines {
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namespace Tegra::Engines {
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KeplerMemory::KeplerMemory(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
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KeplerMemory::KeplerMemory(Core::System& system, MemoryManager& memory_manager)
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MemoryManager& memory_manager)
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: system{system}, memory_manager{memory_manager}, upload_state{memory_manager, regs.upload} {}
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: system{system}, rasterizer{rasterizer}, memory_manager{memory_manager} {}
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KeplerMemory::~KeplerMemory() = default;
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KeplerMemory::~KeplerMemory() = default;
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@ -28,46 +27,18 @@ void KeplerMemory::CallMethod(const GPU::MethodCall& method_call) {
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switch (method_call.method) {
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switch (method_call.method) {
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case KEPLERMEMORY_REG_INDEX(exec): {
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case KEPLERMEMORY_REG_INDEX(exec): {
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ProcessExec();
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upload_state.ProcessExec(regs.exec.linear != 0);
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break;
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break;
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}
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}
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case KEPLERMEMORY_REG_INDEX(data): {
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case KEPLERMEMORY_REG_INDEX(data): {
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ProcessData(method_call.argument, method_call.IsLastCall());
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bool is_last_call = method_call.IsLastCall();
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upload_state.ProcessData(method_call.argument, is_last_call);
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if (is_last_call) {
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system.GPU().Maxwell3D().dirty_flags.OnMemoryWrite();
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}
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break;
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break;
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}
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}
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}
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}
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}
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}
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void KeplerMemory::ProcessExec() {
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state.write_offset = 0;
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state.copy_size = regs.line_length_in * regs.line_count;
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state.inner_buffer.resize(state.copy_size);
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}
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void KeplerMemory::ProcessData(u32 data, bool is_last_call) {
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const u32 sub_copy_size = std::min(4U, state.copy_size - state.write_offset);
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std::memcpy(&state.inner_buffer[state.write_offset], ®s.data, sub_copy_size);
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state.write_offset += sub_copy_size;
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if (is_last_call) {
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const GPUVAddr address{regs.dest.Address()};
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if (regs.exec.linear != 0) {
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memory_manager.WriteBlock(address, state.inner_buffer.data(), state.copy_size);
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} else {
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UNIMPLEMENTED_IF(regs.dest.z != 0);
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UNIMPLEMENTED_IF(regs.dest.depth != 1);
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UNIMPLEMENTED_IF(regs.dest.BlockWidth() != 1);
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UNIMPLEMENTED_IF(regs.dest.BlockDepth() != 1);
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const std::size_t dst_size = Tegra::Texture::CalculateSize(
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true, 1, regs.dest.width, regs.dest.height, 1, regs.dest.BlockHeight(), 1);
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std::vector<u8> tmp_buffer(dst_size);
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memory_manager.ReadBlock(address, tmp_buffer.data(), dst_size);
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Tegra::Texture::SwizzleKepler(regs.dest.width, regs.dest.height, regs.dest.x,
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regs.dest.y, regs.dest.BlockHeight(), state.copy_size,
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state.inner_buffer.data(), tmp_buffer.data());
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memory_manager.WriteBlock(address, tmp_buffer.data(), dst_size);
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}
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system.GPU().Maxwell3D().dirty_flags.OnMemoryWrite();
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}
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}
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} // namespace Tegra::Engines
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} // namespace Tegra::Engines
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@ -10,6 +10,7 @@
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#include "common/bit_field.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "common/common_types.h"
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#include "video_core/engines/engine_upload.h"
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#include "video_core/gpu.h"
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#include "video_core/gpu.h"
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namespace Core {
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namespace Core {
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@ -20,10 +21,6 @@ namespace Tegra {
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class MemoryManager;
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class MemoryManager;
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}
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}
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namespace VideoCore {
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class RasterizerInterface;
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}
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namespace Tegra::Engines {
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namespace Tegra::Engines {
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#define KEPLERMEMORY_REG_INDEX(field_name) \
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#define KEPLERMEMORY_REG_INDEX(field_name) \
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@ -31,8 +28,7 @@ namespace Tegra::Engines {
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class KeplerMemory final {
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class KeplerMemory final {
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public:
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public:
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KeplerMemory(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
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KeplerMemory(Core::System& system, MemoryManager& memory_manager);
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MemoryManager& memory_manager);
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~KeplerMemory();
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~KeplerMemory();
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/// Write the value to the register identified by method.
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/// Write the value to the register identified by method.
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@ -45,42 +41,7 @@ public:
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struct {
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struct {
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INSERT_PADDING_WORDS(0x60);
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INSERT_PADDING_WORDS(0x60);
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u32 line_length_in;
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Upload::Data upload;
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u32 line_count;
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struct {
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u32 address_high;
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u32 address_low;
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u32 pitch;
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union {
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BitField<0, 4, u32> block_width;
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BitField<4, 4, u32> block_height;
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BitField<8, 4, u32> block_depth;
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};
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u32 width;
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u32 height;
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u32 depth;
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u32 z;
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u32 x;
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u32 y;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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u32 BlockWidth() const {
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return 1U << block_width.Value();
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}
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u32 BlockHeight() const {
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return 1U << block_height.Value();
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}
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u32 BlockDepth() const {
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return 1U << block_depth.Value();
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}
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} dest;
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struct {
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struct {
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union {
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union {
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@ -96,28 +57,17 @@ public:
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};
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};
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} regs{};
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} regs{};
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struct {
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u32 write_offset = 0;
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u32 copy_size = 0;
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std::vector<u8> inner_buffer;
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} state{};
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private:
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private:
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Core::System& system;
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Core::System& system;
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VideoCore::RasterizerInterface& rasterizer;
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MemoryManager& memory_manager;
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MemoryManager& memory_manager;
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Upload::State upload_state;
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void ProcessExec();
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void ProcessData(u32 data, bool is_last_call);
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};
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(KeplerMemory::Regs, field_name) == position * 4, \
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static_assert(offsetof(KeplerMemory::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(line_length_in, 0x60);
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ASSERT_REG_POSITION(upload, 0x60);
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ASSERT_REG_POSITION(line_count, 0x61);
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ASSERT_REG_POSITION(dest, 0x62);
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ASSERT_REG_POSITION(exec, 0x6C);
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ASSERT_REG_POSITION(exec, 0x6C);
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ASSERT_REG_POSITION(data, 0x6D);
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ASSERT_REG_POSITION(data, 0x6D);
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#undef ASSERT_REG_POSITION
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#undef ASSERT_REG_POSITION
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@ -37,7 +37,7 @@ GPU::GPU(Core::System& system, VideoCore::RendererBase& renderer) : renderer{ren
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fermi_2d = std::make_unique<Engines::Fermi2D>(rasterizer, *memory_manager);
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fermi_2d = std::make_unique<Engines::Fermi2D>(rasterizer, *memory_manager);
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kepler_compute = std::make_unique<Engines::KeplerCompute>(*memory_manager);
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kepler_compute = std::make_unique<Engines::KeplerCompute>(*memory_manager);
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maxwell_dma = std::make_unique<Engines::MaxwellDMA>(system, rasterizer, *memory_manager);
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maxwell_dma = std::make_unique<Engines::MaxwellDMA>(system, rasterizer, *memory_manager);
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kepler_memory = std::make_unique<Engines::KeplerMemory>(system, rasterizer, *memory_manager);
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kepler_memory = std::make_unique<Engines::KeplerMemory>(system, *memory_manager);
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}
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}
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GPU::~GPU() = default;
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GPU::~GPU() = default;
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