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shader_decode: Implement SSY and SYNC

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This commit is contained in:
ReinUsesLisp 2018-12-15 03:18:25 -03:00
parent abdbafbc20
commit 97f33f00cf
1 changed files with 19 additions and 0 deletions
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19
src/video_core/shader/decode/other.cpp
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@ -57,6 +57,25 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
bb.push_back(Operation(OperationCode::Bra, Immediate(target))); bb.push_back(Operation(OperationCode::Bra, Immediate(target)));
break; break;
} }
case OpCode::Id::SSY: {
UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0,
"Constant buffer flow is not supported");
// The SSY opcode tells the GPU where to re-converge divergent execution paths, it sets the
// target of the jump that the SYNC instruction will make. The SSY opcode has a similar
// structure to the BRA opcode.
bb.push_back(Operation(OperationCode::Ssy, Immediate(pc + instr.bra.GetBranchTarget())));
break;
}
case OpCode::Id::SYNC: {
const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "SYNC condition code used: {}",
static_cast<u32>(cc));
// The SYNC opcode jumps to the address previously set by the SSY opcode
bb.push_back(Operation(OperationCode::Sync));
break;
}
case OpCode::Id::IPA: { case OpCode::Id::IPA: {
const auto& attribute = instr.attribute.fmt28; const auto& attribute = instr.attribute.fmt28;
const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(), const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(),