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VideoCore: Split shader output writing from semantic loading
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parent
335df895b9
commit
92bf5c88e6
3 changed files with 24 additions and 24 deletions
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@ -151,10 +151,11 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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g_debug_context->OnEvent(DebugContext::Event::VertexShaderInvocation,
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static_cast<void*>(&immediate_input));
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Shader::UnitState shader_unit;
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Shader::AttributeBuffer output{};
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shader_unit.LoadInput(regs.vs, immediate_input);
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shader_engine->Run(g_state.vs, shader_unit);
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auto output_vertex = Shader::OutputVertex::FromRegisters(
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shader_unit.registers.output, regs, regs.vs.output_mask);
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shader_unit.WriteOutput(regs.vs, output);
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// Send to renderer
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using Pica::Shader::OutputVertex;
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@ -163,7 +164,8 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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VideoCore::g_renderer->Rasterizer()->AddTriangle(v0, v1, v2);
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};
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g_state.primitive_assembler.SubmitVertex(output_vertex, AddTriangle);
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g_state.primitive_assembler.SubmitVertex(
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Shader::OutputVertex::FromAttributeBuffer(regs, output), AddTriangle);
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}
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}
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}
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@ -281,7 +283,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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if (!vertex_cache_hit) {
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// Initialize data for the current vertex
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Shader::AttributeBuffer input;
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Shader::AttributeBuffer input, output{};
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loader.LoadVertex(base_address, index, vertex, input, memory_accesses);
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// Send to vertex shader
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@ -290,10 +292,10 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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(void*)&input);
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shader_unit.LoadInput(regs.vs, input);
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shader_engine->Run(g_state.vs, shader_unit);
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shader_unit.WriteOutput(regs.vs, output);
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// Retrieve vertex from register data
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output_vertex = Shader::OutputVertex::FromRegisters(shader_unit.registers.output,
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regs, regs.vs.output_mask);
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output_vertex = Shader::OutputVertex::FromAttributeBuffer(regs, output);
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if (is_indexed) {
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vertex_cache[vertex_cache_pos] = output_vertex;
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@ -4,6 +4,7 @@
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#include <cmath>
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#include <cstring>
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#include "common/bit_set.h"
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#include "common/logging/log.h"
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#include "common/microprofile.h"
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#include "video_core/pica.h"
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@ -19,22 +20,13 @@ namespace Pica {
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namespace Shader {
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OutputVertex OutputVertex::FromRegisters(Math::Vec4<float24> output_regs[16], const Regs& regs,
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u32 output_mask) {
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OutputVertex OutputVertex::FromAttributeBuffer(const Regs& regs, AttributeBuffer& input) {
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// Setup output data
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OutputVertex ret;
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// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
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// figure out what those circumstances are and enable the remaining outputs then.
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unsigned index = 0;
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for (unsigned i = 0; i < 7; ++i) {
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if (index >= regs.vs_output_total)
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break;
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if ((output_mask & (1 << i)) == 0)
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continue;
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const auto& output_register_map = regs.vs_output_attributes[index];
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unsigned int num_attributes = regs.vs_output_total;
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for (unsigned int i = 0; i < num_attributes; ++i) {
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const auto& output_register_map = regs.vs_output_attributes[i];
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u32 semantics[4] = {output_register_map.map_x, output_register_map.map_y,
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output_register_map.map_z, output_register_map.map_w};
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@ -42,15 +34,13 @@ OutputVertex OutputVertex::FromRegisters(Math::Vec4<float24> output_regs[16], co
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for (unsigned comp = 0; comp < 4; ++comp) {
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float24* out = ((float24*)&ret) + semantics[comp];
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if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
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*out = output_regs[i][comp];
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*out = input.attr[i][comp];
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} else {
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// Zero output so that attributes which aren't output won't have denormals in them,
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// which would slow us down later.
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memset(out, 0, sizeof(*out));
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}
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}
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index++;
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}
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// The hardware takes the absolute and saturates vertex colors like this, *before* doing
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@ -80,6 +70,13 @@ void UnitState::LoadInput(const Regs::ShaderConfig& config, const AttributeBuffe
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}
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}
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void UnitState::WriteOutput(const Regs::ShaderConfig& config, AttributeBuffer& output) {
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unsigned int output_i = 0;
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for (unsigned int reg : Common::BitSet<u32>(config.output_mask)) {
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output.attr[output_i++] = registers.output[reg];
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}
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}
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MICROPROFILE_DEFINE(GPU_Shader, "GPU", "Shader", MP_RGB(50, 50, 240));
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#ifdef ARCHITECTURE_x86_64
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@ -74,8 +74,7 @@ struct OutputVertex {
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return ret;
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}
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static OutputVertex FromRegisters(Math::Vec4<float24> output_regs[16], const Regs& regs,
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u32 output_mask);
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static OutputVertex FromAttributeBuffer(const Regs& regs, AttributeBuffer& output);
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};
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static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD");
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static_assert(sizeof(OutputVertex) == 32 * sizeof(float), "OutputVertex has invalid size");
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@ -141,6 +140,8 @@ struct UnitState {
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* @param input Attribute buffer to load into the input registers.
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*/
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void LoadInput(const Regs::ShaderConfig& config, const AttributeBuffer& input);
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void WriteOutput(const Regs::ShaderConfig& config, AttributeBuffer& output);
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};
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struct ShaderSetup {
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