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GPU: Implemented the ISETP_R and ISETP_C shader instructions.
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2 changed files with 48 additions and 0 deletions
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@ -238,6 +238,16 @@ union Instruction {
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BitField<56, 1, u64> neg_b;
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} fsetp;
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union {
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BitField<0, 3, u64> pred0;
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BitField<3, 3, u64> pred3;
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BitField<39, 3, u64> pred39;
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BitField<42, 1, u64> neg_pred;
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BitField<45, 2, PredOperation> op;
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BitField<48, 1, u64> is_signed;
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BitField<49, 3, PredCondition> cond;
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} isetp;
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union {
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BitField<39, 3, u64> pred39;
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BitField<42, 1, u64> neg_pred;
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@ -1017,6 +1017,44 @@ private:
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}
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break;
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}
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case OpCode::Type::IntegerSetPredicate: {
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std::string op_a = regs.GetRegisterAsInteger(instr.gpr8, 0, instr.isetp.is_signed);
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std::string op_b{};
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ASSERT_MSG(!instr.is_b_imm, "ISETP_IMM not implemented");
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if (instr.is_b_gpr) {
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op_b += regs.GetRegisterAsInteger(instr.gpr20, 0, instr.isetp.is_signed);
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} else {
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// TODO(Subv): This family of instructions don't store to a GPR, but GetUniform
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// needs to know the type of the output register.
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op_b += regs.GetUniform(instr.uniform, instr.gpr0);
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}
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using Tegra::Shader::Pred;
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// We can't use the constant predicate as destination.
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ASSERT(instr.isetp.pred3 != static_cast<u64>(Pred::UnusedIndex));
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std::string second_pred =
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GetPredicateCondition(instr.isetp.pred39, instr.isetp.neg_pred != 0);
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std::string comparator = GetPredicateComparison(instr.isetp.cond);
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std::string combiner = GetPredicateCombiner(instr.isetp.op);
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std::string predicate = '(' + op_a + ") " + comparator + " (" + op_b + ')';
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// Set the primary predicate to the result of Predicate OP SecondPredicate
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SetPredicate(instr.isetp.pred3,
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'(' + predicate + ") " + combiner + " (" + second_pred + ')');
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if (instr.isetp.pred0 != static_cast<u64>(Pred::UnusedIndex)) {
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// Set the secondary predicate to the result of !Predicate OP SecondPredicate,
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// if enabled
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SetPredicate(instr.isetp.pred0,
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"!(" + predicate + ") " + combiner + " (" + second_pred + ')');
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}
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break;
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}
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case OpCode::Type::FloatSet: {
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std::string op_a = instr.fset.neg_a ? "-" : "";
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op_a += regs.GetRegisterAsFloat(instr.gpr8);
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