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streamline cdma_pusher/command_classes
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parent
ac265a72ce
commit
77564f987c
5 changed files with 34 additions and 85 deletions
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@ -38,45 +38,42 @@ CDmaPusher::CDmaPusher(GPU& gpu_)
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CDmaPusher::~CDmaPusher() = default;
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void CDmaPusher::ProcessEntries(ChCommandHeaderList&& entries) {
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std::vector<u32> values(entries.size());
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std::memcpy(values.data(), entries.data(), entries.size() * sizeof(u32));
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for (const u32 value : values) {
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for (const auto& value : entries) {
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if (mask != 0) {
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const auto lbs = static_cast<u32>(std::countr_zero(mask));
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mask &= ~(1U << lbs);
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ExecuteCommand(static_cast<u32>(offset + lbs), value);
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ExecuteCommand(offset + lbs, value.raw);
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continue;
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} else if (count != 0) {
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--count;
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ExecuteCommand(static_cast<u32>(offset), value);
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ExecuteCommand(offset, value.raw);
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if (incrementing) {
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++offset;
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}
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continue;
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}
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const auto mode = static_cast<ChSubmissionMode>((value >> 28) & 0xf);
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const auto mode = value.submission_mode.Value();
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switch (mode) {
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case ChSubmissionMode::SetClass: {
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mask = value & 0x3f;
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offset = (value >> 16) & 0xfff;
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current_class = static_cast<ChClassId>((value >> 6) & 0x3ff);
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mask = value.value & 0x3f;
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offset = value.method_offset;
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current_class = static_cast<ChClassId>((value.value >> 6) & 0x3ff);
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break;
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}
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case ChSubmissionMode::Incrementing:
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case ChSubmissionMode::NonIncrementing:
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count = value & 0xffff;
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offset = (value >> 16) & 0xfff;
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count = value.value;
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offset = value.method_offset;
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incrementing = mode == ChSubmissionMode::Incrementing;
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break;
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case ChSubmissionMode::Mask:
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mask = value & 0xffff;
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offset = (value >> 16) & 0xfff;
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mask = value.value;
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offset = value.method_offset;
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break;
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case ChSubmissionMode::Immediate: {
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const u32 data = value & 0xfff;
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offset = (value >> 16) & 0xfff;
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ExecuteCommand(static_cast<u32>(offset), data);
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const u32 data = value.value & 0xfff;
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offset = value.method_offset;
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ExecuteCommand(offset, data);
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break;
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}
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default:
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@ -89,8 +86,8 @@ void CDmaPusher::ProcessEntries(ChCommandHeaderList&& entries) {
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void CDmaPusher::ExecuteCommand(u32 state_offset, u32 data) {
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switch (current_class) {
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case ChClassId::NvDec:
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ThiStateWrite(nvdec_thi_state, state_offset, {data});
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switch (static_cast<ThiMethod>(state_offset)) {
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ThiStateWrite(nvdec_thi_state, offset, data);
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switch (static_cast<ThiMethod>(offset)) {
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case ThiMethod::IncSyncpt: {
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LOG_DEBUG(Service_NVDRV, "NVDEC Class IncSyncpt Method");
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const auto syncpoint_id = static_cast<u32>(data & 0xFF);
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@ -106,8 +103,8 @@ void CDmaPusher::ExecuteCommand(u32 state_offset, u32 data) {
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case ThiMethod::SetMethod1:
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LOG_DEBUG(Service_NVDRV, "NVDEC method 0x{:X}",
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static_cast<u32>(nvdec_thi_state.method_0));
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nvdec_processor->ProcessMethod(static_cast<Nvdec::Method>(nvdec_thi_state.method_0),
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{data});
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nvdec_processor->ProcessMethod(
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static_cast<Tegra::Nvdec::Method>(nvdec_thi_state.method_0), data);
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break;
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default:
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break;
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@ -131,7 +128,8 @@ void CDmaPusher::ExecuteCommand(u32 state_offset, u32 data) {
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case ThiMethod::SetMethod1:
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LOG_DEBUG(Service_NVDRV, "VIC method 0x{:X}, Args=({})",
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static_cast<u32>(vic_thi_state.method_0), data);
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vic_processor->ProcessMethod(static_cast<Vic::Method>(vic_thi_state.method_0), {data});
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vic_processor->ProcessMethod(static_cast<Tegra::Vic::Method>(vic_thi_state.method_0),
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data);
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break;
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default:
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break;
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@ -140,7 +138,7 @@ void CDmaPusher::ExecuteCommand(u32 state_offset, u32 data) {
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case ChClassId::Host1x:
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// This device is mainly for syncpoint synchronization
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LOG_DEBUG(Service_NVDRV, "Host1X Class Method");
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host1x_processor->ProcessMethod(static_cast<Host1x::Method>(state_offset), {data});
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host1x_processor->ProcessMethod(static_cast<Tegra::Host1x::Method>(offset), data);
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break;
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default:
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UNIMPLEMENTED_MSG("Current class not implemented {:X}", static_cast<u32>(current_class));
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@ -148,10 +146,9 @@ void CDmaPusher::ExecuteCommand(u32 state_offset, u32 data) {
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}
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}
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void CDmaPusher::ThiStateWrite(ThiRegisters& state, u32 state_offset,
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const std::vector<u32>& arguments) {
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u8* const state_offset_ptr = reinterpret_cast<u8*>(&state) + sizeof(u32) * state_offset;
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std::memcpy(state_offset_ptr, arguments.data(), sizeof(u32) * arguments.size());
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void CDmaPusher::ThiStateWrite(ThiRegisters& state, u32 offset, u32 argument) {
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u8* const state_offset = reinterpret_cast<u8*>(&state) + sizeof(u32) * offset;
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std::memcpy(state_offset, &argument, sizeof(u32));
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}
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} // namespace Tegra
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@ -48,16 +48,10 @@ enum class ChClassId : u32 {
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NvDec = 0xf0
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};
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enum class ChMethod : u32 {
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Empty = 0,
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SetMethod = 0x10,
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SetData = 0x11,
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};
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union ChCommandHeader {
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u32 raw;
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BitField<0, 16, u32> value;
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BitField<16, 12, ChMethod> method_offset;
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BitField<16, 12, u32> method_offset;
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BitField<28, 4, ChSubmissionMode> submission_mode;
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};
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static_assert(sizeof(ChCommandHeader) == sizeof(u32), "ChCommand header is an invalid size");
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@ -107,7 +101,7 @@ private:
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void ExecuteCommand(u32 state_offset, u32 data);
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/// Write arguments value to the ThiRegisters member at the specified offset
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void ThiStateWrite(ThiRegisters& state, u32 state_offset, const std::vector<u32>& arguments);
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void ThiStateWrite(ThiRegisters& state, u32 offset, u32 argument);
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GPU& gpu;
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std::shared_ptr<Tegra::Nvdec> nvdec_processor;
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@ -118,8 +112,8 @@ private:
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ThiRegisters vic_thi_state{};
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ThiRegisters nvdec_thi_state{};
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s32 count{};
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s32 offset{};
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u32 count{};
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u32 offset{};
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u32 mask{};
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bool incrementing{};
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};
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@ -12,16 +12,16 @@ Nvdec::Nvdec(GPU& gpu_) : gpu(gpu_), codec(std::make_unique<Codec>(gpu)) {}
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Nvdec::~Nvdec() = default;
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void Nvdec::ProcessMethod(Method method, const std::vector<u32>& arguments) {
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void Nvdec::ProcessMethod(Method method, u32 argument) {
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if (method == Method::SetVideoCodec) {
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codec->StateWrite(static_cast<u32>(method), arguments[0]);
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codec->StateWrite(static_cast<u32>(method), argument);
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} else {
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codec->StateWrite(static_cast<u32>(method), static_cast<u64>(arguments[0]) << 8);
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codec->StateWrite(static_cast<u32>(method), static_cast<u64>(argument) << 8);
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}
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switch (method) {
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case Method::SetVideoCodec:
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codec->SetTargetCodec(static_cast<NvdecCommon::VideoCodec>(arguments[0]));
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codec->SetTargetCodec(static_cast<NvdecCommon::VideoCodec>(argument));
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break;
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case Method::Execute:
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Execute();
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@ -23,7 +23,7 @@ public:
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~Nvdec();
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/// Writes the method into the state, Invoke Execute() if encountered
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void ProcessMethod(Method method, const std::vector<u32>& arguments);
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void ProcessMethod(Method method, u32 argument);
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/// Return most recently decoded frame
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[[nodiscard]] AVFramePtr GetFrame();
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@ -15,43 +15,6 @@ namespace Tegra {
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class GPU;
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class Nvdec;
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struct PlaneOffsets {
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u32 luma_offset{};
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u32 chroma_u_offset{};
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u32 chroma_v_offset{};
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};
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struct VicRegisters {
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INSERT_PADDING_WORDS(64);
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u32 nop{};
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INSERT_PADDING_WORDS(15);
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u32 pm_trigger{};
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INSERT_PADDING_WORDS(47);
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u32 set_application_id{};
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u32 set_watchdog_timer{};
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INSERT_PADDING_WORDS(17);
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u32 context_save_area{};
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u32 context_switch{};
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INSERT_PADDING_WORDS(43);
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u32 execute{};
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INSERT_PADDING_WORDS(63);
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std::array<std::array<PlaneOffsets, 8>, 8> surfacex_slots{};
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u32 picture_index{};
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u32 control_params{};
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u32 config_struct_offset{};
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u32 filter_struct_offset{};
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u32 palette_offset{};
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u32 hist_offset{};
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u32 context_id{};
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u32 fce_ucode_size{};
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PlaneOffsets output_surface{};
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u32 fce_ucode_offset{};
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INSERT_PADDING_WORDS(4);
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std::array<u32, 8> slot_context_id{};
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INSERT_PADDING_WORDS(16);
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};
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static_assert(sizeof(VicRegisters) == 0x7A0, "VicRegisters is an invalid size");
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class Vic {
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public:
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enum class Method : u32 {
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~Vic();
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/// Write to the device state.
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void ProcessMethod(Method method, const std::vector<u32>& arguments);
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void ProcessMethod(Method method, u32 argument);
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private:
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void Execute();
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void VicStateWrite(u32 offset, u32 arguments);
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VicRegisters vic_state{};
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enum class VideoPixelFormat : u64_le {
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RGBA8 = 0x1f,
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BGRA8 = 0x20,
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@ -88,8 +48,6 @@ private:
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BitField<9, 2, u64_le> chroma_loc_vert;
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BitField<11, 4, u64_le> block_linear_kind;
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BitField<15, 4, u64_le> block_linear_height_log2;
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BitField<19, 3, u64_le> reserved0;
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BitField<22, 10, u64_le> reserved1;
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BitField<32, 14, u64_le> surface_width_minus1;
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BitField<46, 14, u64_le> surface_height_minus1;
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};
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