mirror of
https://github.com/yuzu-mirror/yuzu.git
synced 2024-09-07 11:19:08 +01:00
shader: Add NVN storage buffer fallbacks
When we can't track the SSBO origin of a global memory instruction, leave it as a global memory operation and assume these pointers are in the NVN storage buffer slots, then apply a linear search in the shader's runtime.
This commit is contained in:
parent
6325601947
commit
7018e524f5
9 changed files with 214 additions and 62 deletions
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@ -411,6 +411,7 @@ EmitContext::EmitContext(const Profile& profile_, IR::Program& program, u32& bin
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DefineTextures(program.info, binding);
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DefineImages(program.info, binding);
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DefineAttributeMemAccess(program.info);
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DefineGlobalMemoryFunctions(program.info);
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DefineLabels(program);
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}
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@ -762,6 +763,82 @@ void EmitContext::DefineAttributeMemAccess(const Info& info) {
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}
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}
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void EmitContext::DefineGlobalMemoryFunctions(const Info& info) {
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if (!info.uses_global_memory) {
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return;
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}
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using DefPtr = Id StorageDefinitions::*;
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const Id zero{u32_zero_value};
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const auto define_body{[&](DefPtr ssbo_member, Id addr, Id element_pointer, u32 shift,
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auto&& callback) {
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AddLabel();
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const size_t num_buffers{info.storage_buffers_descriptors.size()};
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for (size_t index = 0; index < num_buffers; ++index) {
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const auto& ssbo{info.storage_buffers_descriptors[index]};
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const Id ssbo_addr_cbuf_offset{Const(ssbo.cbuf_offset / 8)};
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const Id ssbo_size_cbuf_offset{Const(ssbo.cbuf_offset / 4 + 2)};
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const Id ssbo_addr_pointer{OpAccessChain(
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uniform_types.U32x2, cbufs[ssbo.cbuf_index].U32x2, zero, ssbo_addr_cbuf_offset)};
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const Id ssbo_size_pointer{OpAccessChain(uniform_types.U32, cbufs[ssbo.cbuf_index].U32,
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zero, ssbo_size_cbuf_offset)};
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const Id ssbo_addr{OpBitcast(U64, OpLoad(U32[2], ssbo_addr_pointer))};
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const Id ssbo_size{OpUConvert(U64, OpLoad(U32[1], ssbo_size_pointer))};
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const Id ssbo_end{OpIAdd(U64, ssbo_addr, ssbo_size)};
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const Id cond{OpLogicalAnd(U1, OpUGreaterThanEqual(U1, addr, ssbo_addr),
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OpULessThan(U1, addr, ssbo_end))};
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const Id then_label{OpLabel()};
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const Id else_label{OpLabel()};
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OpSelectionMerge(else_label, spv::SelectionControlMask::MaskNone);
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OpBranchConditional(cond, then_label, else_label);
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AddLabel(then_label);
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const Id ssbo_id{ssbos[index].*ssbo_member};
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const Id ssbo_offset{OpUConvert(U32[1], OpISub(U64, addr, ssbo_addr))};
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const Id ssbo_index{OpShiftRightLogical(U32[1], ssbo_offset, Const(shift))};
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const Id ssbo_pointer{OpAccessChain(element_pointer, ssbo_id, zero, ssbo_index)};
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callback(ssbo_pointer);
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AddLabel(else_label);
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}
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}};
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const auto define_load{[&](DefPtr ssbo_member, Id element_pointer, Id type, u32 shift) {
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const Id function_type{TypeFunction(type, U64)};
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const Id func_id{OpFunction(type, spv::FunctionControlMask::MaskNone, function_type)};
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const Id addr{OpFunctionParameter(U64)};
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define_body(ssbo_member, addr, element_pointer, shift,
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[&](Id ssbo_pointer) { OpReturnValue(OpLoad(type, ssbo_pointer)); });
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OpReturnValue(ConstantNull(type));
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OpFunctionEnd();
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return func_id;
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}};
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const auto define_write{[&](DefPtr ssbo_member, Id element_pointer, Id type, u32 shift) {
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const Id function_type{TypeFunction(void_id, U64, type)};
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const Id func_id{OpFunction(void_id, spv::FunctionControlMask::MaskNone, function_type)};
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const Id addr{OpFunctionParameter(U64)};
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const Id data{OpFunctionParameter(type)};
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define_body(ssbo_member, addr, element_pointer, shift, [&](Id ssbo_pointer) {
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OpStore(ssbo_pointer, data);
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OpReturn();
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});
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OpReturn();
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OpFunctionEnd();
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return func_id;
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}};
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const auto define{
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[&](DefPtr ssbo_member, const StorageTypeDefinition& type_def, Id type, size_t size) {
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const Id element_type{type_def.element};
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const u32 shift{static_cast<u32>(std::countr_zero(size))};
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const Id load_func{define_load(ssbo_member, element_type, type, shift)};
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const Id write_func{define_write(ssbo_member, element_type, type, shift)};
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return std::make_pair(load_func, write_func);
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}};
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std::tie(load_global_func_u32, write_global_func_u32) =
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define(&StorageDefinitions::U32, storage_types.U32, U32[1], sizeof(u32));
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std::tie(load_global_func_u32x2, write_global_func_u32x2) =
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define(&StorageDefinitions::U32x2, storage_types.U32x2, U32[2], sizeof(u32[2]));
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std::tie(load_global_func_u32x4, write_global_func_u32x4) =
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define(&StorageDefinitions::U32x4, storage_types.U32x4, U32[4], sizeof(u32[4]));
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}
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void EmitContext::DefineConstantBuffers(const Info& info, u32& binding) {
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if (info.constant_buffer_descriptors.empty()) {
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return;
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@ -224,6 +224,13 @@ public:
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Id f32x2_min_cas{};
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Id f32x2_max_cas{};
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Id load_global_func_u32{};
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Id load_global_func_u32x2{};
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Id load_global_func_u32x4{};
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Id write_global_func_u32{};
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Id write_global_func_u32x2{};
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Id write_global_func_u32x4{};
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Id input_position{};
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std::array<Id, 32> input_generics{};
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@ -255,6 +262,7 @@ private:
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void DefineTextures(const Info& info, u32& binding);
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void DefineImages(const Info& info, u32& binding);
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void DefineAttributeMemAccess(const Info& info);
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void DefineGlobalMemoryFunctions(const Info& info);
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void DefineLabels(IR::Program& program);
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void DefineInputs(const Info& info);
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@ -84,16 +84,16 @@ void EmitLoadGlobalU8(EmitContext& ctx);
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void EmitLoadGlobalS8(EmitContext& ctx);
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void EmitLoadGlobalU16(EmitContext& ctx);
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void EmitLoadGlobalS16(EmitContext& ctx);
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void EmitLoadGlobal32(EmitContext& ctx);
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void EmitLoadGlobal64(EmitContext& ctx);
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void EmitLoadGlobal128(EmitContext& ctx);
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Id EmitLoadGlobal32(EmitContext& ctx, Id address);
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Id EmitLoadGlobal64(EmitContext& ctx, Id address);
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Id EmitLoadGlobal128(EmitContext& ctx, Id address);
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void EmitWriteGlobalU8(EmitContext& ctx);
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void EmitWriteGlobalS8(EmitContext& ctx);
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void EmitWriteGlobalU16(EmitContext& ctx);
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void EmitWriteGlobalS16(EmitContext& ctx);
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void EmitWriteGlobal32(EmitContext& ctx);
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void EmitWriteGlobal64(EmitContext& ctx);
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void EmitWriteGlobal128(EmitContext& ctx);
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void EmitWriteGlobal32(EmitContext& ctx, Id address, Id value);
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void EmitWriteGlobal64(EmitContext& ctx, Id address, Id value);
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void EmitWriteGlobal128(EmitContext& ctx, Id address, Id value);
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Id EmitLoadStorageU8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitLoadStorageS8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitLoadStorageU16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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@ -277,9 +277,9 @@ Id EmitFPIsNan16(EmitContext& ctx, Id value);
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Id EmitFPIsNan32(EmitContext& ctx, Id value);
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Id EmitFPIsNan64(EmitContext& ctx, Id value);
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Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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void EmitIAdd64(EmitContext& ctx);
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Id EmitIAdd64(EmitContext& ctx, Id a, Id b);
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Id EmitISub32(EmitContext& ctx, Id a, Id b);
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void EmitISub64(EmitContext& ctx);
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Id EmitISub64(EmitContext& ctx, Id a, Id b);
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Id EmitIMul32(EmitContext& ctx, Id a, Id b);
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Id EmitINeg32(EmitContext& ctx, Id value);
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Id EmitINeg64(EmitContext& ctx, Id value);
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@ -55,16 +55,16 @@ Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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return result;
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}
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void EmitIAdd64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitIAdd64(EmitContext& ctx, Id a, Id b) {
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return ctx.OpIAdd(ctx.U64, a, b);
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}
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Id EmitISub32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpISub(ctx.U32[1], a, b);
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}
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void EmitISub64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitISub64(EmitContext& ctx, Id a, Id b) {
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return ctx.OpISub(ctx.U64, a, b);
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}
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Id EmitIMul32(EmitContext& ctx, Id a, Id b) {
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@ -64,16 +64,16 @@ void EmitLoadGlobalS16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitLoadGlobal32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitLoadGlobal32(EmitContext& ctx, Id address) {
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return ctx.OpFunctionCall(ctx.U32[1], ctx.load_global_func_u32, address);
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}
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void EmitLoadGlobal64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitLoadGlobal64(EmitContext& ctx, Id address) {
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return ctx.OpFunctionCall(ctx.U32[2], ctx.load_global_func_u32x2, address);
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}
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void EmitLoadGlobal128(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitLoadGlobal128(EmitContext& ctx, Id address) {
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return ctx.OpFunctionCall(ctx.U32[4], ctx.load_global_func_u32x4, address);
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}
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void EmitWriteGlobalU8(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteGlobal32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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void EmitWriteGlobal32(EmitContext& ctx, Id address, Id value) {
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ctx.OpFunctionCall(ctx.void_id, ctx.write_global_func_u32, address, value);
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}
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void EmitWriteGlobal64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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void EmitWriteGlobal64(EmitContext& ctx, Id address, Id value) {
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ctx.OpFunctionCall(ctx.void_id, ctx.write_global_func_u32x2, address, value);
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}
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void EmitWriteGlobal128(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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void EmitWriteGlobal128(EmitContext& ctx, Id address, Id value) {
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ctx.OpFunctionCall(ctx.void_id, ctx.write_global_func_u32x4, address, value);
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}
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Id EmitLoadStorageU8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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@ -60,6 +60,48 @@ void CollectInterpolationInfo(Environment& env, IR::Program& program) {
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}();
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}
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}
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void AddNVNStorageBuffers(IR::Program& program) {
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if (!program.info.uses_global_memory) {
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return;
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}
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const u32 driver_cbuf{0};
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const u32 descriptor_size{0x10};
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const u32 num_buffers{16};
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const u32 base{[&] {
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switch (program.stage) {
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case Stage::VertexA:
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case Stage::VertexB:
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return 0x110u;
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case Stage::TessellationControl:
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return 0x210u;
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case Stage::TessellationEval:
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return 0x310u;
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case Stage::Geometry:
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return 0x410u;
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case Stage::Fragment:
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return 0x510u;
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case Stage::Compute:
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return 0x310u;
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}
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throw InvalidArgument("Invalid stage {}", program.stage);
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}()};
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auto& descs{program.info.storage_buffers_descriptors};
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for (u32 index = 0; index < num_buffers; ++index) {
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const u32 offset{base + index * descriptor_size};
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const auto it{std::ranges::find(descs, offset, &StorageBufferDescriptor::cbuf_offset)};
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if (it != descs.end()) {
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continue;
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}
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// Assume these are written for now
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descs.push_back({
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.cbuf_index = driver_cbuf,
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.cbuf_offset = offset,
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.count = 1,
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.is_written = true,
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});
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}
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}
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} // Anonymous namespace
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IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Block>& block_pool,
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Optimization::VerificationPass(program);
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Optimization::CollectShaderInfoPass(env, program);
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CollectInterpolationInfo(env, program);
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AddNVNStorageBuffers(program);
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return program;
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}
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@ -187,6 +187,8 @@ void VisitUsages(Info& info, IR::Inst& inst) {
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case IR::Opcode::FPUnordGreaterThanEqual16:
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case IR::Opcode::FPIsNan16:
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case IR::Opcode::GlobalAtomicAddF16x2:
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case IR::Opcode::GlobalAtomicMinF16x2:
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case IR::Opcode::GlobalAtomicMaxF16x2:
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case IR::Opcode::StorageAtomicAddF16x2:
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case IR::Opcode::StorageAtomicMinF16x2:
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case IR::Opcode::StorageAtomicMaxF16x2:
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@ -373,12 +375,63 @@ void VisitUsages(Info& info, IR::Inst& inst) {
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case IR::Opcode::StorageAtomicAnd64:
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case IR::Opcode::StorageAtomicOr64:
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case IR::Opcode::StorageAtomicXor64:
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case IR::Opcode::StorageAtomicExchange64:
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info.uses_int64 = true;
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break;
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default:
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break;
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}
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switch (inst.GetOpcode()) {
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case IR::Opcode::LoadGlobalU8:
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case IR::Opcode::LoadGlobalS8:
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case IR::Opcode::LoadGlobalU16:
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case IR::Opcode::LoadGlobalS16:
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case IR::Opcode::LoadGlobal32:
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case IR::Opcode::LoadGlobal64:
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case IR::Opcode::LoadGlobal128:
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case IR::Opcode::WriteGlobalU8:
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case IR::Opcode::WriteGlobalS8:
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case IR::Opcode::WriteGlobalU16:
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case IR::Opcode::WriteGlobalS16:
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case IR::Opcode::WriteGlobal32:
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case IR::Opcode::WriteGlobal64:
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case IR::Opcode::WriteGlobal128:
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case IR::Opcode::GlobalAtomicIAdd32:
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case IR::Opcode::GlobalAtomicSMin32:
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case IR::Opcode::GlobalAtomicUMin32:
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case IR::Opcode::GlobalAtomicSMax32:
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case IR::Opcode::GlobalAtomicUMax32:
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case IR::Opcode::GlobalAtomicInc32:
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case IR::Opcode::GlobalAtomicDec32:
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case IR::Opcode::GlobalAtomicAnd32:
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case IR::Opcode::GlobalAtomicOr32:
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case IR::Opcode::GlobalAtomicXor32:
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case IR::Opcode::GlobalAtomicExchange32:
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case IR::Opcode::GlobalAtomicIAdd64:
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case IR::Opcode::GlobalAtomicSMin64:
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case IR::Opcode::GlobalAtomicUMin64:
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case IR::Opcode::GlobalAtomicSMax64:
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case IR::Opcode::GlobalAtomicUMax64:
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case IR::Opcode::GlobalAtomicAnd64:
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case IR::Opcode::GlobalAtomicOr64:
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case IR::Opcode::GlobalAtomicXor64:
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case IR::Opcode::GlobalAtomicExchange64:
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case IR::Opcode::GlobalAtomicAddF32:
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case IR::Opcode::GlobalAtomicAddF16x2:
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case IR::Opcode::GlobalAtomicAddF32x2:
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case IR::Opcode::GlobalAtomicMinF16x2:
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case IR::Opcode::GlobalAtomicMinF32x2:
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case IR::Opcode::GlobalAtomicMaxF16x2:
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case IR::Opcode::GlobalAtomicMaxF32x2:
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info.uses_int64 = true;
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info.uses_global_memory = true;
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info.used_constant_buffer_types |= IR::Type::U32 | IR::Type::U32x2;
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info.used_storage_buffer_types |= IR::Type::U32 | IR::Type::U32x2 | IR::Type::U32x4;
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break;
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default:
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break;
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}
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switch (inst.GetOpcode()) {
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case IR::Opcode::DemoteToHelperInvocation:
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info.uses_demote_to_helper_invocation = true;
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break;
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@ -11,6 +11,7 @@
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#include <boost/container/flat_set.hpp>
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#include <boost/container/small_vector.hpp>
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#include "common/alignment.h"
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#include "shader_recompiler/frontend/ir/basic_block.h"
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#include "shader_recompiler/frontend/ir/breadth_first_search.h"
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#include "shader_recompiler/frontend/ir/ir_emitter.h"
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@ -244,39 +245,6 @@ bool MeetsBias(const StorageBufferAddr& storage_buffer, const Bias& bias) noexce
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storage_buffer.offset < bias.offset_end;
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}
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/// Discards a global memory operation, reads return zero and writes are ignored
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void DiscardGlobalMemory(IR::Block& block, IR::Inst& inst) {
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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const IR::Value zero{u32{0}};
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switch (inst.GetOpcode()) {
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case IR::Opcode::LoadGlobalS8:
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case IR::Opcode::LoadGlobalU8:
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case IR::Opcode::LoadGlobalS16:
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case IR::Opcode::LoadGlobalU16:
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case IR::Opcode::LoadGlobal32:
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inst.ReplaceUsesWith(zero);
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break;
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case IR::Opcode::LoadGlobal64:
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inst.ReplaceUsesWith(IR::Value{ir.CompositeConstruct(zero, zero)});
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break;
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case IR::Opcode::LoadGlobal128:
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inst.ReplaceUsesWith(IR::Value{ir.CompositeConstruct(zero, zero, zero, zero)});
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break;
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case IR::Opcode::WriteGlobalS8:
|
||||
case IR::Opcode::WriteGlobalU8:
|
||||
case IR::Opcode::WriteGlobalS16:
|
||||
case IR::Opcode::WriteGlobalU16:
|
||||
case IR::Opcode::WriteGlobal32:
|
||||
case IR::Opcode::WriteGlobal64:
|
||||
case IR::Opcode::WriteGlobal128:
|
||||
inst.Invalidate();
|
||||
break;
|
||||
default:
|
||||
throw LogicError("Invalid opcode to discard its global memory operation {}",
|
||||
inst.GetOpcode());
|
||||
}
|
||||
}
|
||||
|
||||
struct LowAddrInfo {
|
||||
IR::U32 value;
|
||||
s32 imm_offset;
|
||||
|
@ -350,6 +318,10 @@ std::optional<StorageBufferAddr> Track(const IR::Value& value, const Bias* bias)
|
|||
.index{index.U32()},
|
||||
.offset{offset.U32()},
|
||||
};
|
||||
if (!Common::IsAligned(storage_buffer.offset, 16)) {
|
||||
// The SSBO pointer has to be aligned
|
||||
return std::nullopt;
|
||||
}
|
||||
if (bias && !MeetsBias(storage_buffer, *bias)) {
|
||||
// We have to blacklist some addresses in case we wrongly
|
||||
// point to them
|
||||
|
@ -372,19 +344,17 @@ void CollectStorageBuffers(IR::Block& block, IR::Inst& inst, StorageInfo& info)
|
|||
// Track the low address of the instruction
|
||||
const std::optional<LowAddrInfo> low_addr_info{TrackLowAddress(&inst)};
|
||||
if (!low_addr_info) {
|
||||
DiscardGlobalMemory(block, inst);
|
||||
// Failed to track the low address, use NVN fallbacks
|
||||
return;
|
||||
}
|
||||
// First try to find storage buffers in the NVN address
|
||||
const IR::U32 low_addr{low_addr_info->value};
|
||||
std::optional storage_buffer{Track(low_addr, &nvn_bias)};
|
||||
std::optional<StorageBufferAddr> storage_buffer{Track(low_addr, &nvn_bias)};
|
||||
if (!storage_buffer) {
|
||||
// If it fails, track without a bias
|
||||
storage_buffer = Track(low_addr, nullptr);
|
||||
if (!storage_buffer) {
|
||||
// If that also failed, drop the global memory usage
|
||||
// LOG_ERROR
|
||||
DiscardGlobalMemory(block, inst);
|
||||
// If that also fails, use NVN fallbacks
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -162,6 +162,7 @@ struct Info {
|
|||
bool uses_atomic_f32x2_min{};
|
||||
bool uses_atomic_f32x2_max{};
|
||||
bool uses_int64_bit_atomics{};
|
||||
bool uses_global_memory{};
|
||||
|
||||
IR::Type used_constant_buffer_types{};
|
||||
IR::Type used_storage_buffer_types{};
|
||||
|
|
Loading…
Reference in a new issue