Make a GPU class in VideoCore to contain the GPU state.

Also moved the GPU MemoryManager class to video_core since it makes more sense for it to be there.
This commit is contained in:
Subv 2018-02-11 23:44:12 -05:00
parent e01a8f2187
commit 6cddf9d88e
20 changed files with 125 additions and 76 deletions

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@ -139,8 +139,6 @@ add_library(core STATIC
hle/service/nvdrv/devices/nvmap.h
hle/service/nvdrv/interface.cpp
hle/service/nvdrv/interface.h
hle/service/nvdrv/memory_manager.cpp
hle/service/nvdrv/memory_manager.h
hle/service/nvdrv/nvdrv.cpp
hle/service/nvdrv/nvdrv.h
hle/service/nvdrv/nvmemp.cpp

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@ -154,6 +154,8 @@ System::ResultStatus System::Init(EmuWindow* emu_window, u32 system_mode) {
break;
}
gpu_core = std::make_unique<Tegra::GPU>();
telemetry_session = std::make_unique<Core::TelemetrySession>();
CoreTiming::Init();

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@ -11,6 +11,7 @@
#include "core/memory.h"
#include "core/perf_stats.h"
#include "core/telemetry_session.h"
#include "video_core/gpu.h"
class EmuWindow;
class ARM_Interface;
@ -102,6 +103,10 @@ public:
return *cpu_core;
}
Tegra::GPU& GPU() {
return *gpu_core;
}
PerfStats perf_stats;
FrameLimiter frame_limiter;
@ -138,6 +143,8 @@ private:
///< ARM11 CPU core
std::unique_ptr<ARM_Interface> cpu_core;
std::unique_ptr<Tegra::GPU> gpu_core;
/// When true, signals that a reschedule should happen
bool reschedule_pending{};

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@ -4,6 +4,7 @@
#include "common/assert.h"
#include "common/logging/log.h"
#include "core/core.h"
#include "core/hle/service/nvdrv/devices/nvhost_as_gpu.h"
#include "core/hle/service/nvdrv/devices/nvmap.h"
@ -44,11 +45,12 @@ u32 nvhost_as_gpu::AllocateSpace(const std::vector<u8>& input, std::vector<u8>&
LOG_DEBUG(Service_NVDRV, "called, pages=%x, page_size=%x, flags=%x", params.pages,
params.page_size, params.flags);
auto& gpu = Core::System::GetInstance().GPU();
const u64 size{static_cast<u64>(params.pages) * static_cast<u64>(params.page_size)};
if (params.flags & 1) {
params.offset = memory_manager->AllocateSpace(params.offset, size, 1);
params.offset = gpu.memory_manager->AllocateSpace(params.offset, size, 1);
} else {
params.offset = memory_manager->AllocateSpace(size, params.align);
params.offset = gpu.memory_manager->AllocateSpace(size, params.align);
}
std::memcpy(output.data(), &params, output.size());
@ -71,10 +73,12 @@ u32 nvhost_as_gpu::MapBufferEx(const std::vector<u8>& input, std::vector<u8>& ou
auto object = nvmap_dev->GetObject(params.nvmap_handle);
ASSERT(object);
auto& gpu = Core::System::GetInstance().GPU();
if (params.flags & 1) {
params.offset = memory_manager->MapBufferEx(object->addr, params.offset, object->size);
params.offset = gpu.memory_manager->MapBufferEx(object->addr, params.offset, object->size);
} else {
params.offset = memory_manager->MapBufferEx(object->addr, object->size);
params.offset = gpu.memory_manager->MapBufferEx(object->addr, object->size);
}
std::memcpy(output.data(), &params, output.size());

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@ -10,7 +10,6 @@
#include "common/common_types.h"
#include "common/swap.h"
#include "core/hle/service/nvdrv/devices/nvdevice.h"
#include "core/hle/service/nvdrv/memory_manager.h"
namespace Service {
namespace Nvidia {
@ -20,8 +19,7 @@ class nvmap;
class nvhost_as_gpu final : public nvdevice {
public:
nvhost_as_gpu(std::shared_ptr<nvmap> nvmap_dev, std::shared_ptr<MemoryManager> memory_manager)
: nvmap_dev(std::move(nvmap_dev)), memory_manager(std::move(memory_manager)) {}
nvhost_as_gpu(std::shared_ptr<nvmap> nvmap_dev) : nvmap_dev(std::move(nvmap_dev)) {}
~nvhost_as_gpu() override = default;
u32 ioctl(Ioctl command, const std::vector<u8>& input, std::vector<u8>& output) override;
@ -100,7 +98,6 @@ private:
u32 GetVARegions(const std::vector<u8>& input, std::vector<u8>& output);
std::shared_ptr<nvmap> nvmap_dev;
std::shared_ptr<MemoryManager> memory_manager;
};
} // namespace Devices

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@ -5,8 +5,8 @@
#include <map>
#include "common/assert.h"
#include "common/logging/log.h"
#include "core/core.h"
#include "core/hle/service/nvdrv/devices/nvhost_gpu.h"
#include "video_core/command_processor.h"
namespace Service {
namespace Nvidia {
@ -131,9 +131,8 @@ u32 nvhost_gpu::SubmitGPFIFO(const std::vector<u8>& input, std::vector<u8>& outp
std::memcpy(&entries[0], &input.data()[sizeof(IoctlSubmitGpfifo)],
params.num_entries * sizeof(IoctlGpfifoEntry));
for (auto entry : entries) {
VAddr va_addr = memory_manager->PhysicalToVirtualAddress(entry.Address());
Tegra::CommandProcessor::ProcessCommandList(va_addr, entry.sz);
// TODO(ogniK): Process these
VAddr va_addr = entry.Address();
Core::System::GetInstance().GPU().ProcessCommandList(va_addr, entry.sz);
}
params.fence_out.id = 0;
params.fence_out.value = 0;

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@ -9,7 +9,6 @@
#include "common/common_types.h"
#include "common/swap.h"
#include "core/hle/service/nvdrv/devices/nvdevice.h"
#include "core/hle/service/nvdrv/memory_manager.h"
namespace Service {
namespace Nvidia {
@ -21,8 +20,7 @@ constexpr u32 NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO(0x8);
class nvhost_gpu final : public nvdevice {
public:
nvhost_gpu(std::shared_ptr<nvmap> nvmap_dev, std::shared_ptr<MemoryManager> memory_manager)
: nvmap_dev(std::move(nvmap_dev)), memory_manager(std::move(memory_manager)) {}
nvhost_gpu(std::shared_ptr<nvmap> nvmap_dev) : nvmap_dev(std::move(nvmap_dev)) {}
~nvhost_gpu() override = default;
u32 ioctl(Ioctl command, const std::vector<u8>& input, std::vector<u8>& output) override;
@ -139,7 +137,6 @@ private:
u32 SubmitGPFIFO(const std::vector<u8>& input, std::vector<u8>& output);
std::shared_ptr<nvmap> nvmap_dev;
std::shared_ptr<MemoryManager> memory_manager;
};
} // namespace Devices

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@ -11,7 +11,6 @@
#include "core/hle/service/nvdrv/devices/nvhost_gpu.h"
#include "core/hle/service/nvdrv/devices/nvmap.h"
#include "core/hle/service/nvdrv/interface.h"
#include "core/hle/service/nvdrv/memory_manager.h"
#include "core/hle/service/nvdrv/nvdrv.h"
#include "core/hle/service/nvdrv/nvmemp.h"
@ -32,10 +31,8 @@ void InstallInterfaces(SM::ServiceManager& service_manager) {
Module::Module() {
auto nvmap_dev = std::make_shared<Devices::nvmap>();
auto memory_manager = std::make_shared<MemoryManager>();
devices["/dev/nvhost-as-gpu"] =
std::make_shared<Devices::nvhost_as_gpu>(nvmap_dev, memory_manager);
devices["/dev/nvhost-gpu"] = std::make_shared<Devices::nvhost_gpu>(nvmap_dev, memory_manager);
devices["/dev/nvhost-as-gpu"] = std::make_shared<Devices::nvhost_as_gpu>(nvmap_dev);
devices["/dev/nvhost-gpu"] = std::make_shared<Devices::nvhost_gpu>(nvmap_dev);
devices["/dev/nvhost-ctrl-gpu"] = std::make_shared<Devices::nvhost_ctrl_gpu>();
devices["/dev/nvmap"] = nvmap_dev;
devices["/dev/nvdisp_disp0"] = std::make_shared<Devices::nvdisp_disp0>(nvmap_dev);

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@ -7,6 +7,9 @@ add_library(video_core STATIC
engines/maxwell_3d.h
engines/maxwell_compute.cpp
engines/maxwell_compute.h
gpu.h
memory_manager.cpp
memory_manager.h
renderer_base.cpp
renderer_base.h
renderer_opengl/gl_resource_manager.h

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@ -16,30 +16,18 @@
#include "video_core/engines/fermi_2d.h"
#include "video_core/engines/maxwell_3d.h"
#include "video_core/engines/maxwell_compute.h"
#include "video_core/gpu.h"
#include "video_core/renderer_base.h"
#include "video_core/video_core.h"
namespace Tegra {
namespace CommandProcessor {
enum class BufferMethods {
BindObject = 0,
CountBufferMethods = 0x100,
};
enum class EngineID {
FERMI_TWOD_A = 0x902D, // 2D Engine
MAXWELL_B = 0xB197, // 3D Engine
MAXWELL_COMPUTE_B = 0xB1C0,
KEPLER_INLINE_TO_MEMORY_B = 0xA140,
MAXWELL_DMA_COPY_A = 0xB0B5,
};
// Mapping of subchannels to their bound engine ids.
static std::unordered_map<u32, EngineID> bound_engines;
static void WriteReg(u32 method, u32 subchannel, u32 value) {
void GPU::WriteReg(u32 method, u32 subchannel, u32 value) {
LOG_WARNING(HW_GPU, "Processing method %08X on subchannel %u value %08X", method, subchannel,
value);
@ -63,22 +51,25 @@ static void WriteReg(u32 method, u32 subchannel, u32 value) {
switch (engine) {
case EngineID::FERMI_TWOD_A:
Engines::Fermi2D::WriteReg(method, value);
fermi_2d->WriteReg(method, value);
break;
case EngineID::MAXWELL_B:
Engines::Maxwell3D::WriteReg(method, value);
maxwell_3d->WriteReg(method, value);
break;
case EngineID::MAXWELL_COMPUTE_B:
Engines::MaxwellCompute::WriteReg(method, value);
maxwell_compute->WriteReg(method, value);
break;
default:
UNIMPLEMENTED();
}
}
void ProcessCommandList(VAddr address, u32 size) {
VAddr current_addr = address;
while (current_addr < address + size * sizeof(CommandHeader)) {
void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
// TODO(Subv): PhysicalToVirtualAddress is a misnomer, it converts a GPU VAddr into an
// application VAddr.
const VAddr head_address = memory_manager->PhysicalToVirtualAddress(address);
VAddr current_addr = head_address;
while (current_addr < head_address + size * sizeof(CommandHeader)) {
const CommandHeader header = {Memory::Read32(current_addr)};
current_addr += sizeof(u32);
@ -125,6 +116,4 @@ void ProcessCommandList(VAddr address, u32 size) {
}
}
} // namespace CommandProcessor
} // namespace Tegra

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@ -10,8 +10,6 @@
namespace Tegra {
namespace CommandProcessor {
enum class SubmissionMode : u32 {
IncreasingOld = 0,
Increasing = 1,
@ -38,6 +36,4 @@ static_assert(sizeof(CommandHeader) == sizeof(u32), "CommandHeader has incorrect
void ProcessCommandList(VAddr address, u32 size);
} // namespace CommandProcessor
} // namespace Tegra

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@ -6,10 +6,8 @@
namespace Tegra {
namespace Engines {
namespace Fermi2D {
void WriteReg(u32 method, u32 value) {}
void Fermi2D::WriteReg(u32 method, u32 value) {}
} // namespace Fermi2D
} // namespace Engines
} // namespace Tegra

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@ -8,11 +8,15 @@
namespace Tegra {
namespace Engines {
namespace Fermi2D {
void WriteReg(u32 method, u32 value);
class Fermi2D final {
public:
Fermi2D() = default;
~Fermi2D() = default;
} // namespace Fermi2D
/// Write the value to the register identified by method.
void WriteReg(u32 method, u32 value);
};
} // namespace Engines
} // namespace Tegra

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@ -6,10 +6,8 @@
namespace Tegra {
namespace Engines {
namespace Maxwell3D {
void WriteReg(u32 method, u32 value) {}
void Maxwell3D::WriteReg(u32 method, u32 value) {}
} // namespace Maxwell3D
} // namespace Engines
} // namespace Tegra

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@ -8,11 +8,15 @@
namespace Tegra {
namespace Engines {
namespace Maxwell3D {
void WriteReg(u32 method, u32 value);
class Maxwell3D final {
public:
Maxwell3D() = default;
~Maxwell3D() = default;
} // namespace Maxwell3D
/// Write the value to the register identified by method.
void WriteReg(u32 method, u32 value);
};
} // namespace Engines
} // namespace Tegra

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@ -6,10 +6,8 @@
namespace Tegra {
namespace Engines {
namespace MaxwellCompute {
void WriteReg(u32 method, u32 value) {}
void MaxwellCompute::WriteReg(u32 method, u32 value) {}
} // namespace MaxwellCompute
} // namespace Engines
} // namespace Tegra

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@ -8,11 +8,15 @@
namespace Tegra {
namespace Engines {
namespace MaxwellCompute {
void WriteReg(u32 method, u32 value);
class MaxwellCompute final {
public:
MaxwellCompute() = default;
~MaxwellCompute() = default;
} // namespace MaxwellCompute
/// Write the value to the register identified by method.
void WriteReg(u32 method, u32 value);
};
} // namespace Engines
} // namespace Tegra

55
src/video_core/gpu.h Normal file
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@ -0,0 +1,55 @@
// Copyright 2018 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#pragma once
#include <memory>
#include <unordered_map>
#include "common/common_types.h"
#include "video_core/engines/fermi_2d.h"
#include "video_core/engines/maxwell_3d.h"
#include "video_core/engines/maxwell_compute.h"
#include "video_core/memory_manager.h"
namespace Tegra {
enum class EngineID {
FERMI_TWOD_A = 0x902D, // 2D Engine
MAXWELL_B = 0xB197, // 3D Engine
MAXWELL_COMPUTE_B = 0xB1C0,
KEPLER_INLINE_TO_MEMORY_B = 0xA140,
MAXWELL_DMA_COPY_A = 0xB0B5,
};
class GPU final {
public:
GPU() {
memory_manager = std::make_unique<MemoryManager>();
maxwell_3d = std::make_unique<Engines::Maxwell3D>();
fermi_2d = std::make_unique<Engines::Fermi2D>();
maxwell_compute = std::make_unique<Engines::MaxwellCompute>();
}
~GPU() = default;
/// Processes a command list stored at the specified address in GPU memory.
void ProcessCommandList(GPUVAddr address, u32 size);
std::unique_ptr<MemoryManager> memory_manager;
private:
/// Writes a single register in the engine bound to the specified subchannel
void WriteReg(u32 method, u32 subchannel, u32 value);
/// Mapping of command subchannels to their bound engine ids.
std::unordered_map<u32, EngineID> bound_engines;
/// 3D engine
std::unique_ptr<Engines::Maxwell3D> maxwell_3d;
/// 2D engine
std::unique_ptr<Engines::Fermi2D> fermi_2d;
/// Compute engine
std::unique_ptr<Engines::MaxwellCompute> maxwell_compute;
};
} // namespace Tegra

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@ -3,10 +3,9 @@
// Refer to the license.txt file included.
#include "common/assert.h"
#include "core/hle/service/nvdrv/memory_manager.h"
#include "video_core/memory_manager.h"
namespace Service {
namespace Nvidia {
namespace Tegra {
PAddr MemoryManager::AllocateSpace(u64 size, u64 align) {
boost::optional<PAddr> paddr = FindFreeBlock(size, align);
@ -108,5 +107,4 @@ VAddr& MemoryManager::PageSlot(PAddr paddr) {
return (*block)[(paddr >> Memory::PAGE_BITS) & PAGE_BLOCK_MASK];
}
} // namespace Nvidia
} // namespace Service
} // namespace Tegra

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@ -9,8 +9,10 @@
#include "common/common_types.h"
#include "core/memory.h"
namespace Service {
namespace Nvidia {
namespace Tegra {
/// Virtual addresses in the GPU's memory map are 64 bit.
using GPUVAddr = u64;
class MemoryManager final {
public:
@ -44,5 +46,4 @@ private:
std::array<std::unique_ptr<PageBlock>, PAGE_TABLE_SIZE> page_table{};
};
} // namespace Nvidia
} // namespace Service
} // namespace Tegra