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https://github.com/yuzu-mirror/yuzu.git
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shader: Implement FSWZADD
This commit is contained in:
parent
34aba9627a
commit
6c51f49632
14 changed files with 87 additions and 4 deletions
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@ -89,6 +89,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/floating_point_multiply.cpp
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frontend/maxwell/translate/impl/floating_point_multiply.cpp
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frontend/maxwell/translate/impl/floating_point_range_reduction.cpp
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frontend/maxwell/translate/impl/floating_point_range_reduction.cpp
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frontend/maxwell/translate/impl/floating_point_set_predicate.cpp
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frontend/maxwell/translate/impl/floating_point_set_predicate.cpp
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frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp
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frontend/maxwell/translate/impl/half_floating_point_add.cpp
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frontend/maxwell/translate/impl/half_floating_point_add.cpp
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frontend/maxwell/translate/impl/half_floating_point_fused_multiply_add.cpp
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frontend/maxwell/translate/impl/half_floating_point_fused_multiply_add.cpp
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frontend/maxwell/translate/impl/half_floating_point_helper.cpp
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frontend/maxwell/translate/impl/half_floating_point_helper.cpp
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@ -393,6 +393,14 @@ void EmitContext::DefineInputs(const Info& info) {
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subgroup_local_invocation_id =
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subgroup_local_invocation_id =
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DefineInput(*this, U32[1], spv::BuiltIn::SubgroupLocalInvocationId);
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DefineInput(*this, U32[1], spv::BuiltIn::SubgroupLocalInvocationId);
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}
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}
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if (info.uses_fswzadd) {
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const Id f32_one{Constant(F32[1], 1.0f)};
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const Id f32_minus_one{Constant(F32[1], -1.0f)};
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const Id f32_zero{Constant(F32[1], 0.0f)};
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fswzadd_lut_a = ConstantComposite(F32[4], f32_minus_one, f32_one, f32_minus_one, f32_zero);
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fswzadd_lut_b =
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ConstantComposite(F32[4], f32_minus_one, f32_minus_one, f32_one, f32_minus_one);
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}
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if (info.loads_position) {
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if (info.loads_position) {
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const bool is_fragment{stage != Stage::Fragment};
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const bool is_fragment{stage != Stage::Fragment};
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const spv::BuiltIn built_in{is_fragment ? spv::BuiltIn::Position : spv::BuiltIn::FragCoord};
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const spv::BuiltIn built_in{is_fragment ? spv::BuiltIn::Position : spv::BuiltIn::FragCoord};
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@ -103,6 +103,8 @@ public:
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Id vertex_index{};
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Id vertex_index{};
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Id base_vertex{};
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Id base_vertex{};
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Id front_face{};
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Id front_face{};
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Id fswzadd_lut_a{};
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Id fswzadd_lut_b{};
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Id local_memory{};
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Id local_memory{};
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@ -397,5 +397,6 @@ Id EmitShuffleDown(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clam
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Id segmentation_mask);
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Id segmentation_mask);
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Id EmitShuffleButterfly(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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Id EmitShuffleButterfly(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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Id segmentation_mask);
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Id segmentation_mask);
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Id EmitFSwizzleAdd(EmitContext& ctx, Id op_a, Id op_b, Id swizzle);
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} // namespace Shader::Backend::SPIRV
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} // namespace Shader::Backend::SPIRV
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@ -132,4 +132,20 @@ Id EmitShuffleButterfly(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id
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return SelectValue(ctx, in_range, value, src_thread_id);
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return SelectValue(ctx, in_range, value, src_thread_id);
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}
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}
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Id EmitFSwizzleAdd(EmitContext& ctx, Id op_a, Id op_b, Id swizzle) {
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const Id three{ctx.Constant(ctx.U32[1], 3)};
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Id mask{ctx.OpLoad(ctx.U32[1], ctx.subgroup_local_invocation_id)};
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mask = ctx.OpBitwiseAnd(ctx.U32[1], mask, three);
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mask = ctx.OpShiftLeftLogical(ctx.U32[1], mask, ctx.Constant(ctx.U32[1], 1));
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mask = ctx.OpShiftRightLogical(ctx.U32[1], swizzle, mask);
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mask = ctx.OpBitwiseAnd(ctx.U32[1], mask, three);
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const Id modifier_a{ctx.OpVectorExtractDynamic(ctx.F32[1], ctx.fswzadd_lut_a, mask)};
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const Id modifier_b{ctx.OpVectorExtractDynamic(ctx.F32[1], ctx.fswzadd_lut_b, mask)};
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const Id result_a{ctx.OpFMul(ctx.F32[1], op_a, modifier_a)};
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const Id result_b{ctx.OpFMul(ctx.F32[1], op_b, modifier_b)};
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return ctx.OpFAdd(ctx.F32[1], result_a, result_b);
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}
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} // namespace Shader::Backend::SPIRV
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} // namespace Shader::Backend::SPIRV
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@ -1602,4 +1602,7 @@ U32 IREmitter::ShuffleButterfly(const IR::U32& value, const IR::U32& index, cons
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const IR::U32& seg_mask) {
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const IR::U32& seg_mask) {
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return Inst<U32>(Opcode::ShuffleButterfly, value, index, clamp, seg_mask);
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return Inst<U32>(Opcode::ShuffleButterfly, value, index, clamp, seg_mask);
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}
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}
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F32 IREmitter::FSwizzleAdd(const F32& a, const F32& b, const U32& swizzle, FpControl control) {
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return Inst<F32>(Opcode::FSwizzleAdd, Flags{control}, a, b, swizzle);
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}
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} // namespace Shader::IR
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} // namespace Shader::IR
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@ -277,6 +277,8 @@ public:
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const IR::U32& seg_mask);
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const IR::U32& seg_mask);
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[[nodiscard]] U32 ShuffleButterfly(const IR::U32& value, const IR::U32& index,
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[[nodiscard]] U32 ShuffleButterfly(const IR::U32& value, const IR::U32& index,
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const IR::U32& clamp, const IR::U32& seg_mask);
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const IR::U32& clamp, const IR::U32& seg_mask);
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[[nodiscard]] F32 FSwizzleAdd(const F32& a, const F32& b, const U32& swizzle,
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FpControl control = {});
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private:
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private:
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IR::Block::iterator insertion_point;
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IR::Block::iterator insertion_point;
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@ -408,3 +408,4 @@ OPCODE(ShuffleIndex, U32, U32,
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OPCODE(ShuffleUp, U32, U32, U32, U32, U32, )
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OPCODE(ShuffleUp, U32, U32, U32, U32, U32, )
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OPCODE(ShuffleDown, U32, U32, U32, U32, U32, )
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OPCODE(ShuffleDown, U32, U32, U32, U32, U32, )
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OPCODE(ShuffleButterfly, U32, U32, U32, U32, U32, )
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OPCODE(ShuffleButterfly, U32, U32, U32, U32, U32, )
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OPCODE(FSwizzleAdd, F32, F32, F32, U32, )
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@ -0,0 +1,44 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/common_types.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_encoding.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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void TranslatorVisitor::FSWZADD(u64 insn) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<28, 8, u64> swizzle;
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BitField<38, 1, u64> ndv;
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BitField<39, 2, FpRounding> round;
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BitField<44, 1, u64> ftz;
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BitField<47, 1, u64> cc;
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} const fswzadd{insn};
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if (fswzadd.ndv != 0) {
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throw NotImplementedException("FSWZADD NDV");
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}
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const IR::F32 src_a{GetFloatReg8(insn)};
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const IR::F32 src_b{GetFloatReg20(insn)};
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const IR::U32 swizzle{ir.Imm32(static_cast<u32>(fswzadd.swizzle))};
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const IR::FpControl fp_control{
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.no_contraction{false},
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.rounding{CastFpRounding(fswzadd.round)},
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.fmz_mode{fswzadd.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None},
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};
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const IR::F32 result{ir.FSwizzleAdd(src_a, src_b, swizzle, fp_control)};
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F(fswzadd.dest_reg, result);
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if (fswzadd.cc != 0) {
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throw NotImplementedException("FSWZADD CC");
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}
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}
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} // namespace Shader::Maxwell
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@ -91,6 +91,10 @@ IR::U32 TranslatorVisitor::GetReg39(u64 insn) {
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return X(reg.index);
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return X(reg.index);
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}
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}
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IR::F32 TranslatorVisitor::GetFloatReg8(u64 insn) {
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return ir.BitCast<IR::F32>(GetReg8(insn));
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}
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IR::F32 TranslatorVisitor::GetFloatReg20(u64 insn) {
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IR::F32 TranslatorVisitor::GetFloatReg20(u64 insn) {
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return ir.BitCast<IR::F32>(GetReg20(insn));
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return ir.BitCast<IR::F32>(GetReg20(insn));
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}
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}
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@ -353,6 +353,7 @@ public:
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[[nodiscard]] IR::U32 GetReg8(u64 insn);
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[[nodiscard]] IR::U32 GetReg8(u64 insn);
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[[nodiscard]] IR::U32 GetReg20(u64 insn);
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[[nodiscard]] IR::U32 GetReg20(u64 insn);
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[[nodiscard]] IR::U32 GetReg39(u64 insn);
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[[nodiscard]] IR::U32 GetReg39(u64 insn);
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[[nodiscard]] IR::F32 GetFloatReg8(u64 insn);
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[[nodiscard]] IR::F32 GetFloatReg20(u64 insn);
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[[nodiscard]] IR::F32 GetFloatReg20(u64 insn);
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[[nodiscard]] IR::F32 GetFloatReg39(u64 insn);
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[[nodiscard]] IR::F32 GetFloatReg39(u64 insn);
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[[nodiscard]] IR::F64 GetDoubleReg20(u64 insn);
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[[nodiscard]] IR::F64 GetDoubleReg20(u64 insn);
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@ -89,10 +89,6 @@ void TranslatorVisitor::FCHK_imm(u64) {
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ThrowNotImplemented(Opcode::FCHK_imm);
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ThrowNotImplemented(Opcode::FCHK_imm);
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}
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}
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void TranslatorVisitor::FSWZADD(u64) {
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ThrowNotImplemented(Opcode::FSWZADD);
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}
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void TranslatorVisitor::GETCRSPTR(u64) {
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void TranslatorVisitor::GETCRSPTR(u64) {
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ThrowNotImplemented(Opcode::GETCRSPTR);
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ThrowNotImplemented(Opcode::GETCRSPTR);
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}
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}
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@ -389,6 +389,9 @@ void VisitUsages(Info& info, IR::Inst& inst) {
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case IR::Opcode::SubgroupBallot:
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case IR::Opcode::SubgroupBallot:
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info.uses_subgroup_vote = true;
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info.uses_subgroup_vote = true;
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break;
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break;
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case IR::Opcode::FSwizzleAdd:
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info.uses_fswzadd = true;
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break;
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default:
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default:
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break;
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break;
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}
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}
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@ -94,6 +94,7 @@ struct Info {
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bool uses_sparse_residency{};
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bool uses_sparse_residency{};
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bool uses_demote_to_helper_invocation{};
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bool uses_demote_to_helper_invocation{};
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bool uses_subgroup_vote{};
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bool uses_subgroup_vote{};
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bool uses_fswzadd{};
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IR::Type used_constant_buffer_types{};
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IR::Type used_constant_buffer_types{};
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