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Pica/CommandProcessor: Properly implement shader load destination offset registers.
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parent
67120270f2
commit
6c26ec72a5
2 changed files with 10 additions and 20 deletions
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@ -25,10 +25,6 @@ static int float_regs_counter = 0;
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static u32 uniform_write_buffer[4];
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// Used for VSLoadProgramData and VSLoadSwizzleData
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static u32 vs_binary_write_offset = 0;
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static u32 vs_swizzle_write_offset = 0;
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static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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if (id >= registers.NumIds())
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@ -258,11 +254,6 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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break;
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}
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// Seems to be used to reset the write pointer for VSLoadProgramData
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case PICA_REG_INDEX(vs_program.begin_load):
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vs_binary_write_offset = 0;
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break;
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// Load shader program code
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[0], 0x2cc):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[1], 0x2cd):
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@ -273,16 +264,11 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[6], 0x2d2):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[7], 0x2d3):
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{
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VertexShader::SubmitShaderMemoryChange(vs_binary_write_offset, value);
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vs_binary_write_offset++;
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VertexShader::SubmitShaderMemoryChange(registers.vs_program.offset, value);
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registers.vs_program.offset++;
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break;
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}
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// Seems to be used to reset the write pointer for VSLoadSwizzleData
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case PICA_REG_INDEX(vs_swizzle_patterns.begin_load):
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vs_swizzle_write_offset = 0;
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break;
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// Load swizzle pattern data
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[0], 0x2d6):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[1], 0x2d7):
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@ -293,8 +279,8 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[6], 0x2dc):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[7], 0x2dd):
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{
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VertexShader::SubmitSwizzleDataChange(vs_swizzle_write_offset, value);
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vs_swizzle_write_offset++;
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VertexShader::SubmitSwizzleDataChange(registers.vs_swizzle_patterns.offset, value);
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registers.vs_swizzle_patterns.offset++;
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break;
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}
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@ -678,7 +678,9 @@ struct Regs {
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INSERT_PADDING_WORDS(0x2);
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struct {
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u32 begin_load;
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// Offset of the next instruction to write code to.
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// Incremented with each instruction write.
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u32 offset;
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// Writing to these registers sets the "current" word in the shader program.
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// TODO: It's not clear how the hardware stores what the "current" word is.
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@ -690,7 +692,9 @@ struct Regs {
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// This register group is used to load an internal table of swizzling patterns,
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// which are indexed by each shader instruction to specify vector component swizzling.
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struct {
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u32 begin_load;
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// Offset of the next swizzle pattern to write code to.
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// Incremented with each instruction write.
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u32 offset;
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// Writing to these registers sets the "current" swizzle pattern in the table.
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// TODO: It's not clear how the hardware stores what the "current" swizzle pattern is.
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