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Merge pull request #248 from Subv/cb_data
GPU: Handle writes to the CB_DATA method.
This commit is contained in:
commit
6317a0b2ca
5 changed files with 105 additions and 11 deletions
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@ -7,6 +7,7 @@ add_library(video_core STATIC
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engines/maxwell_3d.h
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engines/maxwell_3d.h
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engines/maxwell_compute.cpp
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engines/maxwell_compute.cpp
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engines/maxwell_compute.h
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engines/maxwell_compute.h
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gpu.cpp
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gpu.h
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gpu.h
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memory_manager.cpp
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memory_manager.cpp
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memory_manager.h
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memory_manager.h
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@ -13,6 +13,7 @@ constexpr u32 MacroRegistersStart = 0xE00;
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const std::unordered_map<u32, Maxwell3D::MethodInfo> Maxwell3D::method_handlers = {
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const std::unordered_map<u32, Maxwell3D::MethodInfo> Maxwell3D::method_handlers = {
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{0xE24, {"SetShader", 5, &Maxwell3D::SetShader}},
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{0xE24, {"SetShader", 5, &Maxwell3D::SetShader}},
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{0xE2A, {"BindStorageBuffer", 1, &Maxwell3D::BindStorageBuffer}},
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};
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};
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Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
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Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
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@ -83,6 +84,25 @@ void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
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ASSERT_MSG(regs.code_address.CodeAddress() == 0, "Unexpected CODE_ADDRESS register value.");
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ASSERT_MSG(regs.code_address.CodeAddress() == 0, "Unexpected CODE_ADDRESS register value.");
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break;
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break;
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}
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}
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[0]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[1]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[2]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[3]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[4]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[5]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[6]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[7]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[8]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[9]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[10]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[11]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[12]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[13]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[14]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[15]): {
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ProcessCBData(value);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[0].raw_config): {
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case MAXWELL3D_REG_INDEX(cb_bind[0].raw_config): {
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ProcessCBBind(Regs::ShaderStage::Vertex);
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ProcessCBBind(Regs::ShaderStage::Vertex);
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break;
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break;
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@ -181,6 +201,26 @@ void Maxwell3D::SetShader(const std::vector<u32>& parameters) {
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ProcessCBBind(shader_stage);
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ProcessCBBind(shader_stage);
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}
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}
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void Maxwell3D::BindStorageBuffer(const std::vector<u32>& parameters) {
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/**
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* Parameters description:
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* [0] = Buffer offset >> 2
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*/
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u32 buffer_offset = parameters[0] << 2;
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// Perform the same operations as the real macro code.
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// Note: This value is hardcoded in the macro's code.
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static constexpr u32 DefaultCBSize = 0x5F00;
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regs.const_buffer.cb_size = DefaultCBSize;
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GPUVAddr address = regs.ssbo_info.BufferAddress();
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regs.const_buffer.cb_address_high = address >> 32;
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regs.const_buffer.cb_address_low = address & 0xFFFFFFFF;
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regs.const_buffer.cb_pos = buffer_offset;
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}
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void Maxwell3D::ProcessCBBind(Regs::ShaderStage stage) {
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void Maxwell3D::ProcessCBBind(Regs::ShaderStage stage) {
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// Bind the buffer currently in CB_ADDRESS to the specified index in the desired shader stage.
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// Bind the buffer currently in CB_ADDRESS to the specified index in the desired shader stage.
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auto& shader = state.shader_stages[static_cast<size_t>(stage)];
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auto& shader = state.shader_stages[static_cast<size_t>(stage)];
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@ -194,5 +234,22 @@ void Maxwell3D::ProcessCBBind(Regs::ShaderStage stage) {
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buffer.size = regs.const_buffer.cb_size;
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buffer.size = regs.const_buffer.cb_size;
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}
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}
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void Maxwell3D::ProcessCBData(u32 value) {
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// Write the input value to the current const buffer at the current position.
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GPUVAddr buffer_address = regs.const_buffer.BufferAddress();
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ASSERT(buffer_address != 0);
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// Don't allow writing past the end of the buffer.
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ASSERT(regs.const_buffer.cb_pos + sizeof(u32) <= regs.const_buffer.cb_size);
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VAddr address =
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memory_manager.PhysicalToVirtualAddress(buffer_address + regs.const_buffer.cb_pos);
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Memory::Write32(address, value);
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// Increment the current buffer position.
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regs.const_buffer.cb_pos = regs.const_buffer.cb_pos + 4;
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}
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} // namespace Engines
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} // namespace Engines
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} // namespace Tegra
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} // namespace Tegra
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@ -166,7 +166,19 @@ public:
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u32 tex_cb_index;
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u32 tex_cb_index;
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INSERT_PADDING_WORDS(0x4B3);
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INSERT_PADDING_WORDS(0x395);
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struct {
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/// Compressed address of a buffer that holds information about bound SSBOs.
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/// This address is usually bound to c0 in the shaders.
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u32 buffer_address;
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GPUVAddr BufferAddress() const {
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return static_cast<GPUVAddr>(buffer_address) << 8;
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}
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} ssbo_info;
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INSERT_PADDING_WORDS(0x11D);
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};
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};
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std::array<u32, NUM_REGS> reg_array;
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std::array<u32, NUM_REGS> reg_array;
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};
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};
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@ -218,6 +230,9 @@ private:
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/// Handles a write to the QUERY_GET register.
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/// Handles a write to the QUERY_GET register.
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void ProcessQueryGet();
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void ProcessQueryGet();
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/// Handles a write to the CB_DATA[i] register.
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void ProcessCBData(u32 value);
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/// Handles a write to the CB_BIND register.
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/// Handles a write to the CB_BIND register.
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void ProcessCBBind(Regs::ShaderStage stage);
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void ProcessCBBind(Regs::ShaderStage stage);
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@ -226,6 +241,7 @@ private:
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/// Method call handlers
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/// Method call handlers
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void SetShader(const std::vector<u32>& parameters);
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void SetShader(const std::vector<u32>& parameters);
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void BindStorageBuffer(const std::vector<u32>& parameters);
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struct MethodInfo {
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struct MethodInfo {
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const char* name;
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const char* name;
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@ -249,6 +265,7 @@ ASSERT_REG_POSITION(shader_config[0], 0x800);
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ASSERT_REG_POSITION(const_buffer, 0x8E0);
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ASSERT_REG_POSITION(const_buffer, 0x8E0);
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ASSERT_REG_POSITION(cb_bind[0], 0x904);
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ASSERT_REG_POSITION(cb_bind[0], 0x904);
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ASSERT_REG_POSITION(tex_cb_index, 0x982);
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ASSERT_REG_POSITION(tex_cb_index, 0x982);
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ASSERT_REG_POSITION(ssbo_info, 0xD18);
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#undef ASSERT_REG_POSITION
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#undef ASSERT_REG_POSITION
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21
src/video_core/gpu.cpp
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21
src/video_core/gpu.cpp
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@ -0,0 +1,21 @@
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_compute.h"
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#include "video_core/gpu.h"
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namespace Tegra {
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GPU::GPU() {
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memory_manager = std::make_unique<MemoryManager>();
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maxwell_3d = std::make_unique<Engines::Maxwell3D>(*memory_manager);
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fermi_2d = std::make_unique<Engines::Fermi2D>();
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maxwell_compute = std::make_unique<Engines::MaxwellCompute>();
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}
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GPU::~GPU() = default;
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} // namespace Tegra
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@ -8,13 +8,16 @@
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#include <unordered_map>
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#include <unordered_map>
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#include <vector>
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#include <vector>
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#include "common/common_types.h"
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#include "common/common_types.h"
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_compute.h"
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#include "video_core/memory_manager.h"
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#include "video_core/memory_manager.h"
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namespace Tegra {
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namespace Tegra {
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namespace Engines {
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class Fermi2D;
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class Maxwell3D;
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class MaxwellCompute;
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} // namespace Engines
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enum class EngineID {
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enum class EngineID {
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FERMI_TWOD_A = 0x902D, // 2D Engine
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FERMI_TWOD_A = 0x902D, // 2D Engine
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MAXWELL_B = 0xB197, // 3D Engine
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MAXWELL_B = 0xB197, // 3D Engine
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@ -25,13 +28,8 @@ enum class EngineID {
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class GPU final {
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class GPU final {
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public:
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public:
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GPU() {
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GPU();
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memory_manager = std::make_unique<MemoryManager>();
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~GPU();
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maxwell_3d = std::make_unique<Engines::Maxwell3D>(*memory_manager);
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fermi_2d = std::make_unique<Engines::Fermi2D>();
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maxwell_compute = std::make_unique<Engines::MaxwellCompute>();
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}
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~GPU() = default;
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/// Processes a command list stored at the specified address in GPU memory.
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/// Processes a command list stored at the specified address in GPU memory.
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void ProcessCommandList(GPUVAddr address, u32 size);
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void ProcessCommandList(GPUVAddr address, u32 size);
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