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https://github.com/yuzu-mirror/yuzu.git
synced 2024-09-07 11:09:09 +01:00
Corrections Half Float operations on const buffers and implement saturation.
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parent
650d9b1044
commit
623b2e4b8f
2 changed files with 16 additions and 15 deletions
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@ -9,6 +9,7 @@
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namespace VideoCommon::Shader {
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namespace VideoCommon::Shader {
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using Tegra::Shader::HalfType;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::OpCode;
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@ -22,7 +23,6 @@ u32 ShaderIR::DecodeArithmeticHalf(NodeBlock& bb, u32 pc) {
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LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName());
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LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName());
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}
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}
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}
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}
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UNIMPLEMENTED_IF_MSG(instr.alu_half.saturate != 0, "Half float saturation not implemented");
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const bool negate_a =
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const bool negate_a =
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opcode->get().GetId() != OpCode::Id::HMUL2_R && instr.alu_half.negate_a != 0;
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opcode->get().GetId() != OpCode::Id::HMUL2_R && instr.alu_half.negate_a != 0;
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@ -32,35 +32,37 @@ u32 ShaderIR::DecodeArithmeticHalf(NodeBlock& bb, u32 pc) {
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Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.alu_half.type_a);
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Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.alu_half.type_a);
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op_a = GetOperandAbsNegHalf(op_a, instr.alu_half.abs_a, negate_a);
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op_a = GetOperandAbsNegHalf(op_a, instr.alu_half.abs_a, negate_a);
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Node op_b = [&]() {
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auto [type_b, op_b] = [&]() -> std::tuple<HalfType, Node> {
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switch (opcode->get().GetId()) {
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switch (opcode->get().GetId()) {
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case OpCode::Id::HADD2_C:
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case OpCode::Id::HADD2_C:
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case OpCode::Id::HMUL2_C:
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case OpCode::Id::HMUL2_C:
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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return {HalfType::F32, GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset())};
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case OpCode::Id::HADD2_R:
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case OpCode::Id::HADD2_R:
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case OpCode::Id::HMUL2_R:
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case OpCode::Id::HMUL2_R:
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return GetRegister(instr.gpr20);
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return {instr.alu_half.type_b, GetRegister(instr.gpr20)};
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default:
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default:
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UNREACHABLE();
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UNREACHABLE();
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return Immediate(0);
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return {HalfType::F32, Immediate(0)};
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}
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}
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}();
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}();
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op_b = UnpackHalfFloat(op_b, instr.alu_half.type_b);
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op_b = UnpackHalfFloat(op_b, type_b);
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op_b = GetOperandAbsNegHalf(op_b, instr.alu_half.abs_b, negate_b);
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// redeclaration to avoid a bug in clang with reusing local bindings in lambdas
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Node op_b_alt = GetOperandAbsNegHalf(op_b, instr.alu_half.abs_b, negate_b);
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Node value = [&]() {
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Node value = [&]() {
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switch (opcode->get().GetId()) {
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switch (opcode->get().GetId()) {
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case OpCode::Id::HADD2_C:
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case OpCode::Id::HADD2_C:
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case OpCode::Id::HADD2_R:
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case OpCode::Id::HADD2_R:
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return Operation(OperationCode::HAdd, PRECISE, op_a, op_b);
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return Operation(OperationCode::HAdd, PRECISE, op_a, op_b_alt);
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case OpCode::Id::HMUL2_C:
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case OpCode::Id::HMUL2_C:
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case OpCode::Id::HMUL2_R:
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case OpCode::Id::HMUL2_R:
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return Operation(OperationCode::HMul, PRECISE, op_a, op_b);
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return Operation(OperationCode::HMul, PRECISE, op_a, op_b_alt);
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default:
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default:
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UNIMPLEMENTED_MSG("Unhandled half float instruction: {}", opcode->get().GetName());
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UNIMPLEMENTED_MSG("Unhandled half float instruction: {}", opcode->get().GetName());
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return Immediate(0);
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return Immediate(0);
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}
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}
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}();
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}();
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value = GetSaturatedHalfFloat(value, instr.alu_half.saturate);
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value = HalfMerge(GetRegister(instr.gpr0), value, instr.alu_half.merge);
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value = HalfMerge(GetRegister(instr.gpr0), value, instr.alu_half.merge);
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SetRegister(bb, instr.gpr0, value);
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SetRegister(bb, instr.gpr0, value);
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@ -34,15 +34,14 @@ u32 ShaderIR::DecodeHfma2(NodeBlock& bb, u32 pc) {
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case OpCode::Id::HFMA2_CR:
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case OpCode::Id::HFMA2_CR:
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neg_b = instr.hfma2.negate_b;
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neg_b = instr.hfma2.negate_b;
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neg_c = instr.hfma2.negate_c;
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neg_c = instr.hfma2.negate_c;
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return {instr.hfma2.saturate, instr.hfma2.type_b,
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return {instr.hfma2.saturate, HalfType::F32,
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GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset()),
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GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset()),
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instr.hfma2.type_reg39, GetRegister(instr.gpr39)};
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instr.hfma2.type_reg39, GetRegister(instr.gpr39)};
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case OpCode::Id::HFMA2_RC:
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case OpCode::Id::HFMA2_RC:
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neg_b = instr.hfma2.negate_b;
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neg_b = instr.hfma2.negate_b;
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neg_c = instr.hfma2.negate_c;
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neg_c = instr.hfma2.negate_c;
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return {instr.hfma2.saturate, instr.hfma2.type_reg39, GetRegister(instr.gpr39),
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return {instr.hfma2.saturate, instr.hfma2.type_reg39, GetRegister(instr.gpr39),
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instr.hfma2.type_b,
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HalfType::F32, GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset())};
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GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset())};
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case OpCode::Id::HFMA2_RR:
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case OpCode::Id::HFMA2_RR:
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neg_b = instr.hfma2.rr.negate_b;
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neg_b = instr.hfma2.rr.negate_b;
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neg_c = instr.hfma2.rr.negate_c;
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neg_c = instr.hfma2.rr.negate_c;
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@ -56,13 +55,13 @@ u32 ShaderIR::DecodeHfma2(NodeBlock& bb, u32 pc) {
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return {false, identity, Immediate(0), identity, Immediate(0)};
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return {false, identity, Immediate(0), identity, Immediate(0)};
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}
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}
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}();
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}();
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UNIMPLEMENTED_IF_MSG(saturate, "HFMA2 saturation is not implemented");
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const Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hfma2.type_a);
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const Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hfma2.type_a);
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op_b = GetOperandAbsNegHalf(UnpackHalfFloat(op_b, type_b), false, neg_b);
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op_b = GetOperandAbsNegHalf(UnpackHalfFloat(op_b, type_b), false, neg_b);
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op_c = GetOperandAbsNegHalf(UnpackHalfFloat(op_c, type_c), false, neg_c);
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op_c = GetOperandAbsNegHalf(UnpackHalfFloat(op_c, type_c), false, neg_c);
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Node value = Operation(OperationCode::HFma, PRECISE, op_a, op_b, op_c);
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Node value = Operation(OperationCode::HFma, PRECISE, op_a, op_b, op_c);
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value = GetSaturatedHalfFloat(value, saturate);
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value = HalfMerge(GetRegister(instr.gpr0), value, instr.hfma2.merge);
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value = HalfMerge(GetRegister(instr.gpr0), value, instr.hfma2.merge);
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SetRegister(bb, instr.gpr0, value);
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SetRegister(bb, instr.gpr0, value);
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