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shader_ir/warp: Implement FSWZADD
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parent
08b2b1080a
commit
56e237d1f9
5 changed files with 44 additions and 0 deletions
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@ -615,6 +615,14 @@ union Instruction {
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BitField<34, 13, u64> mask_imm;
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BitField<34, 13, u64> mask_imm;
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} shfl;
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} shfl;
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union {
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BitField<44, 1, u64> ftz;
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BitField<39, 2, u64> tab5cb8_2;
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BitField<38, 1, u64> ndv;
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BitField<47, 1, u64> cc;
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BitField<28, 8, u64> swizzle;
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} fswzadd;
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union {
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union {
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BitField<8, 8, Register> gpr;
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BitField<8, 8, Register> gpr;
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BitField<20, 24, s64> offset;
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BitField<20, 24, s64> offset;
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@ -1590,6 +1598,7 @@ public:
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DEPBAR,
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DEPBAR,
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VOTE,
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VOTE,
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SHFL,
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SHFL,
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FSWZADD,
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BFE_C,
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BFE_C,
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BFE_R,
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BFE_R,
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BFE_IMM,
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BFE_IMM,
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@ -1888,6 +1897,7 @@ private:
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INST("1111000011110---", Id::DEPBAR, Type::Synch, "DEPBAR"),
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INST("1111000011110---", Id::DEPBAR, Type::Synch, "DEPBAR"),
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INST("0101000011011---", Id::VOTE, Type::Warp, "VOTE"),
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INST("0101000011011---", Id::VOTE, Type::Warp, "VOTE"),
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INST("1110111100010---", Id::SHFL, Type::Warp, "SHFL"),
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INST("1110111100010---", Id::SHFL, Type::Warp, "SHFL"),
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INST("0101000011111---", Id::FSWZADD, Type::Warp, "FSWZADD"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111101001---", Id::LD_S, Type::Memory, "LD_S"),
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INST("1110111101001---", Id::LD_S, Type::Memory, "LD_S"),
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INST("1110111101000---", Id::LD_L, Type::Memory, "LD_L"),
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INST("1110111101000---", Id::LD_L, Type::Memory, "LD_L"),
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@ -1379,6 +1379,20 @@ private:
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return GenerateUnary(operation, "float", Type::Float, type);
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return GenerateUnary(operation, "float", Type::Float, type);
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}
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}
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Expression FSwizzleAdd(Operation operation) {
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const std::string op_a = VisitOperand(operation, 0).AsFloat();
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const std::string op_b = VisitOperand(operation, 1).AsFloat();
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const std::string instr_mask = VisitOperand(operation, 2).AsUint();
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const std::string mask = code.GenerateTemporary();
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code.AddLine("uint {} = {} >> ((gl_SubGroupInvocationARB & 3) << 1);", mask, instr_mask);
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const std::string modifier_a = fmt::format("fswzadd_modifiers_a[{} & 3]", mask);
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const std::string modifier_b = fmt::format("fswzadd_modifiers_b[{} & 3]", mask);
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return {fmt::format("(({} * {}) + ({} * {}))", op_a, modifier_a, op_b, modifier_b),
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Type::Float};
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}
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Expression ICastFloat(Operation operation) {
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Expression ICastFloat(Operation operation) {
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return GenerateUnary(operation, "int", Type::Int, Type::Float);
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return GenerateUnary(operation, "int", Type::Int, Type::Float);
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}
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}
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@ -1991,6 +2005,7 @@ private:
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&GLSLDecompiler::FTrunc,
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&GLSLDecompiler::FTrunc,
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&GLSLDecompiler::FCastInteger<Type::Int>,
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&GLSLDecompiler::FCastInteger<Type::Int>,
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&GLSLDecompiler::FCastInteger<Type::Uint>,
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&GLSLDecompiler::FCastInteger<Type::Uint>,
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&GLSLDecompiler::FSwizzleAdd,
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&GLSLDecompiler::Add<Type::Int>,
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&GLSLDecompiler::Add<Type::Int>,
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&GLSLDecompiler::Mul<Type::Int>,
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&GLSLDecompiler::Mul<Type::Int>,
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@ -2460,6 +2475,9 @@ bvec2 HalfFloatNanComparison(bvec2 comparison, vec2 pair1, vec2 pair2) {
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bvec2 is_nan2 = isnan(pair2);
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bvec2 is_nan2 = isnan(pair2);
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return bvec2(comparison.x || is_nan1.x || is_nan2.x, comparison.y || is_nan1.y || is_nan2.y);
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return bvec2(comparison.x || is_nan1.x || is_nan2.x, comparison.y || is_nan1.y || is_nan2.y);
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}
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}
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const float fswzadd_modifiers_a[] = float[4](-1.0f, 1.0f, -1.0f, 0.0f );
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const float fswzadd_modifiers_b[] = float[4](-1.0f, -1.0f, 1.0f, -1.0f );
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)";
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)";
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}
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}
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@ -783,6 +783,11 @@ private:
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return {};
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return {};
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}
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}
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Id FSwizzleAdd(Operation operation) {
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UNIMPLEMENTED();
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return {};
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}
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Id HNegate(Operation operation) {
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Id HNegate(Operation operation) {
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UNIMPLEMENTED();
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UNIMPLEMENTED();
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return {};
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return {};
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@ -1363,6 +1368,7 @@ private:
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&SPIRVDecompiler::Unary<&Module::OpTrunc, Type::Float>,
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&SPIRVDecompiler::Unary<&Module::OpTrunc, Type::Float>,
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&SPIRVDecompiler::Unary<&Module::OpConvertSToF, Type::Float, Type::Int>,
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&SPIRVDecompiler::Unary<&Module::OpConvertSToF, Type::Float, Type::Int>,
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&SPIRVDecompiler::Unary<&Module::OpConvertUToF, Type::Float, Type::Uint>,
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&SPIRVDecompiler::Unary<&Module::OpConvertUToF, Type::Float, Type::Uint>,
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&SPIRVDecompiler::FSwizzleAdd,
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&SPIRVDecompiler::Binary<&Module::OpIAdd, Type::Int>,
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&SPIRVDecompiler::Binary<&Module::OpIAdd, Type::Int>,
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&SPIRVDecompiler::Binary<&Module::OpIMul, Type::Int>,
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&SPIRVDecompiler::Binary<&Module::OpIMul, Type::Int>,
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@ -94,6 +94,15 @@ u32 ShaderIR::DecodeWarp(NodeBlock& bb, u32 pc) {
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Operation(OperationCode::ShuffleIndexed, GetRegister(instr.gpr8), src_thread_id));
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Operation(OperationCode::ShuffleIndexed, GetRegister(instr.gpr8), src_thread_id));
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break;
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break;
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}
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}
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case OpCode::Id::FSWZADD: {
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UNIMPLEMENTED_IF(instr.fswzadd.ndv);
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Node op_a = GetRegister(instr.gpr8);
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Node op_b = GetRegister(instr.gpr20);
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Node mask = Immediate(static_cast<u32>(instr.fswzadd.swizzle));
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SetRegister(bb, instr.gpr0, Operation(OperationCode::FSwizzleAdd, op_a, op_b, mask));
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break;
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}
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default:
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default:
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UNIMPLEMENTED_MSG("Unhandled warp instruction: {}", opcode->get().GetName());
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UNIMPLEMENTED_MSG("Unhandled warp instruction: {}", opcode->get().GetName());
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break;
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break;
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@ -47,6 +47,7 @@ enum class OperationCode {
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FTrunc, /// (MetaArithmetic, float a) -> float
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FTrunc, /// (MetaArithmetic, float a) -> float
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FCastInteger, /// (MetaArithmetic, int a) -> float
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FCastInteger, /// (MetaArithmetic, int a) -> float
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FCastUInteger, /// (MetaArithmetic, uint a) -> float
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FCastUInteger, /// (MetaArithmetic, uint a) -> float
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FSwizzleAdd, /// (float a, float b, uint mask) -> float
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IAdd, /// (MetaArithmetic, int a, int b) -> int
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IAdd, /// (MetaArithmetic, int a, int b) -> int
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IMul, /// (MetaArithmetic, int a, int b) -> int
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IMul, /// (MetaArithmetic, int a, int b) -> int
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