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gl_rasterizer_cache: Clamp cached surface size to mapped GPU region size.
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parent
37575eae65
commit
4e9683e9d5
2 changed files with 37 additions and 19 deletions
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@ -34,16 +34,29 @@ struct FormatTuple {
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bool compressed;
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};
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static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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auto& gpu{Core::System::GetInstance().GPU()};
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const auto cpu_addr{gpu.MemoryManager().GpuToCpuAddress(gpu_addr)};
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return cpu_addr ? *cpu_addr : 0;
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void SurfaceParams::InitCacheParameters(Tegra::GPUVAddr gpu_addr) {
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auto& memory_manager{Core::System::GetInstance().GPU().MemoryManager()};
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const auto cpu_addr{memory_manager.GpuToCpuAddress(gpu_addr)};
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const auto max_size{memory_manager.GetRegionEnd(gpu_addr) - gpu_addr};
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addr = cpu_addr ? *cpu_addr : 0;
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size_in_bytes_total = SizeInBytesTotal();
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size_in_bytes_2d = SizeInBytes2D();
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// Clamp sizes to mapped GPU memory region
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if (size_in_bytes_2d > max_size) {
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LOG_ERROR(HW_GPU, "Surface size {} exceeds region size {}", size_in_bytes_2d, max_size);
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size_in_bytes_total = max_size;
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size_in_bytes_2d = max_size;
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} else if (size_in_bytes_total > max_size) {
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LOG_ERROR(HW_GPU, "Surface size {} exceeds region size {}", size_in_bytes_total, max_size);
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size_in_bytes_total = max_size;
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}
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}
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/*static*/ SurfaceParams SurfaceParams::CreateForTexture(
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const Tegra::Texture::FullTextureInfo& config, const GLShader::SamplerEntry& entry) {
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SurfaceParams params{};
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params.addr = TryGetCpuAddr(config.tic.Address());
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params.is_tiled = config.tic.IsTiled();
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params.block_width = params.is_tiled ? config.tic.BlockWidth() : 0,
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params.block_height = params.is_tiled ? config.tic.BlockHeight() : 0,
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@ -87,18 +100,18 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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break;
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}
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params.size_in_bytes_total = params.SizeInBytesTotal();
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params.size_in_bytes_2d = params.SizeInBytes2D();
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params.max_mip_level = config.tic.max_mip_level + 1;
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params.rt = {};
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params.InitCacheParameters(config.tic.Address());
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return params;
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}
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/*static*/ SurfaceParams SurfaceParams::CreateForFramebuffer(std::size_t index) {
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const auto& config{Core::System::GetInstance().GPU().Maxwell3D().regs.rt[index]};
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SurfaceParams params{};
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params.addr = TryGetCpuAddr(config.Address());
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params.is_tiled =
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config.memory_layout.type == Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout::BlockLinear;
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params.block_width = 1 << config.memory_layout.block_width;
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@ -112,8 +125,6 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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params.unaligned_height = config.height;
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params.target = SurfaceTarget::Texture2D;
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params.depth = 1;
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params.size_in_bytes_total = params.SizeInBytesTotal();
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params.size_in_bytes_2d = params.SizeInBytes2D();
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params.max_mip_level = 0;
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// Render target specific parameters, not used for caching
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@ -122,6 +133,8 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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params.rt.layer_stride = config.layer_stride;
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params.rt.base_layer = config.base_layer;
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params.InitCacheParameters(config.Address());
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return params;
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}
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@ -130,7 +143,7 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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u32 block_width, u32 block_height, u32 block_depth,
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Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout type) {
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SurfaceParams params{};
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params.addr = TryGetCpuAddr(zeta_address);
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params.is_tiled = type == Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout::BlockLinear;
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params.block_width = 1 << std::min(block_width, 5U);
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params.block_height = 1 << std::min(block_height, 5U);
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@ -143,18 +156,18 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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params.unaligned_height = zeta_height;
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params.target = SurfaceTarget::Texture2D;
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params.depth = 1;
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params.size_in_bytes_total = params.SizeInBytesTotal();
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params.size_in_bytes_2d = params.SizeInBytes2D();
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params.max_mip_level = 0;
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params.rt = {};
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params.InitCacheParameters(zeta_address);
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return params;
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}
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/*static*/ SurfaceParams SurfaceParams::CreateForFermiCopySurface(
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const Tegra::Engines::Fermi2D::Regs::Surface& config) {
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SurfaceParams params{};
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params.addr = TryGetCpuAddr(config.Address());
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params.is_tiled = !config.linear;
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params.block_width = params.is_tiled ? std::min(config.BlockWidth(), 32U) : 0,
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params.block_height = params.is_tiled ? std::min(config.BlockHeight(), 32U) : 0,
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@ -167,11 +180,11 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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params.unaligned_height = config.height;
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params.target = SurfaceTarget::Texture2D;
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params.depth = 1;
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params.size_in_bytes_total = params.SizeInBytesTotal();
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params.size_in_bytes_2d = params.SizeInBytes2D();
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params.max_mip_level = 0;
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params.rt = {};
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params.InitCacheParameters(config.Address());
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return params;
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}
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@ -742,7 +742,9 @@ struct SurfaceParams {
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other.depth);
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}
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VAddr addr;
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/// Initializes parameters for caching, should be called after everything has been initialized
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void InitCacheParameters(Tegra::GPUVAddr gpu_addr);
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bool is_tiled;
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u32 block_width;
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u32 block_height;
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@ -754,11 +756,14 @@ struct SurfaceParams {
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u32 height;
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u32 depth;
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u32 unaligned_height;
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std::size_t size_in_bytes_total;
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std::size_t size_in_bytes_2d;
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SurfaceTarget target;
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u32 max_mip_level;
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// Parameters used for caching
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VAddr addr;
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std::size_t size_in_bytes_total;
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std::size_t size_in_bytes_2d;
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// Render target specific parameters, not used in caching
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struct {
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u32 index;
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