Move ConstBufferAccessor to Maxwell3d, correct mistakes and clang format.

This commit is contained in:
Fernando Sahmkow 2019-04-07 08:30:26 -04:00 committed by FernandoS27
parent 797e351bf8
commit 492040bd9c
9 changed files with 25 additions and 44 deletions

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@ -1,5 +1,4 @@
add_library(video_core STATIC
const_buffer_accessor.h
dma_pusher.cpp
dma_pusher.h
debug_utils/debug_utils.cpp

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@ -1,28 +0,0 @@
#pragma once
#include <cstring>
#include "common/common_types.h"
#include "core/core.h"
#include "video_core/engines/maxwell_3d.h"
#include "video_core/gpu.h"
#include "video_core/memory_manager.h"
namespace Tegra {
namespace ConstBufferAccessor {
template <typename T>
T access(Tegra::Engines::Maxwell3D::Regs::ShaderStage stage, u64 const_buffer, u64 offset) {
auto& gpu = Core::System::GetInstance().GPU();
auto& memory_manager = gpu.MemoryManager();
auto& maxwell3d = gpu.Maxwell3D();
const auto& shader_stage = maxwell3d.state.shader_stages[static_cast<std::size_t>(stage)];
const auto& buffer = shader_stage.const_buffers[const_buffer];
T result;
std::memcpy(&result, memory_manager.GetPointer(buffer.address + offset), sizeof(T));
return result;
}
} // namespace ConstBufferAccessor
} // namespace Tegra

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@ -502,8 +502,8 @@ Texture::FullTextureInfo Maxwell3D::GetTextureInfo(const Texture::TextureHandle
Texture::FullTextureInfo Maxwell3D::GetStageTexture(Regs::ShaderStage stage,
std::size_t offset) const {
auto& shader = state.shader_stages[static_cast<std::size_t>(stage)];
auto& tex_info_buffer = shader.const_buffers[regs.tex_cb_index];
const auto& shader = state.shader_stages[static_cast<std::size_t>(stage)];
const auto& tex_info_buffer = shader.const_buffers[regs.tex_cb_index];
ASSERT(tex_info_buffer.enabled && tex_info_buffer.address != 0);
const GPUVAddr tex_info_address =
@ -529,4 +529,12 @@ void Maxwell3D::ProcessClearBuffers() {
rasterizer.Clear();
}
u32 Maxwell3D::AccessConstBuffer32(Regs::ShaderStage stage, u64 const_buffer, u64 offset) const {
const auto& shader_stage = state.shader_stages[static_cast<std::size_t>(stage)];
const auto& buffer = shader_stage.const_buffers[const_buffer];
u32 result;
std::memcpy(&result, memory_manager.GetPointer(buffer.address + offset), sizeof(u32));
return result;
}
} // namespace Tegra::Engines

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@ -1141,6 +1141,8 @@ public:
/// Returns the texture information for a specific texture in a specific shader stage.
Texture::FullTextureInfo GetStageTexture(Regs::ShaderStage stage, std::size_t offset) const;
u32 AccessConstBuffer32(Regs::ShaderStage stage, u64 const_buffer, u64 offset) const;
/// Memory for macro code - it's undetermined how big this is, however 1MB is much larger than
/// we've seen used.
using MacroMemory = std::array<u32, 0x40000>;

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@ -976,7 +976,7 @@ union Instruction {
BitField<37, 3, TextureProcessMode> process_mode;
bool IsComponentEnabled(std::size_t component) const {
return ((1ull << component) & component_mask) != 0;
return ((1ULL << component) & component_mask) != 0;
}
TextureProcessMode GetTextureProcessMode() const {

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@ -19,7 +19,6 @@
#include "core/core.h"
#include "core/hle/kernel/process.h"
#include "core/settings.h"
#include "video_core/const_buffer_accessor.h"
#include "video_core/engines/maxwell_3d.h"
#include "video_core/renderer_opengl/gl_rasterizer.h"
#include "video_core/renderer_opengl/gl_shader_cache.h"
@ -985,14 +984,13 @@ void RasterizerOpenGL::SetupTextures(Maxwell::ShaderStage stage, const Shader& s
for (u32 bindpoint = 0; bindpoint < entries.size(); ++bindpoint) {
const auto& entry = entries[bindpoint];
Tegra::Texture::FullTextureInfo texture;
if (!entry.IsBindless()) {
texture = maxwell3d.GetStageTexture(stage, entry.GetOffset());
} else {
if (entry.IsBindless()) {
const auto cbuf = entry.GetBindlessCBuf();
Tegra::Texture::TextureHandle tex_handle;
tex_handle.raw =
Tegra::ConstBufferAccessor::access<u32>(stage, cbuf.first, cbuf.second);
tex_handle.raw = maxwell3d.AccessConstBuffer32(stage, cbuf.first, cbuf.second);
texture = maxwell3d.GetTextureInfo(tex_handle, entry.GetOffset());
} else {
texture = maxwell3d.GetStageTexture(stage, entry.GetOffset());
}
const u32 current_bindpoint = base_bindings.sampler + bindpoint;

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@ -328,9 +328,10 @@ std::optional<ShaderDiskCacheDecompiled> ShaderDiskCacheOpenGL::LoadDecompiledEn
file.ReadBytes(&is_bindless, sizeof(u8)) != sizeof(u8)) {
return {};
}
entry.entries.samplers.emplace_back(
static_cast<std::size_t>(offset), static_cast<std::size_t>(index),
static_cast<Tegra::Shader::TextureType>(type), is_array != 0, is_shadow != 0, is_bindless != 0);
entry.entries.samplers.emplace_back(static_cast<std::size_t>(offset),
static_cast<std::size_t>(index),
static_cast<Tegra::Shader::TextureType>(type),
is_array != 0, is_shadow != 0, is_bindless != 0);
}
u32 global_memory_count{};

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@ -153,6 +153,7 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
}
case OpCode::Id::TXQ_B:
is_bindless = true;
[[fallthrough]];
case OpCode::Id::TXQ: {
if (instr.txq.UsesMiscMode(TextureMiscMode::NODEP)) {
LOG_WARNING(HW_GPU, "TXQ.NODEP implementation is incomplete");
@ -193,6 +194,7 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
}
case OpCode::Id::TMML_B:
is_bindless = true;
[[fallthrough]];
case OpCode::Id::TMML: {
UNIMPLEMENTED_IF_MSG(instr.tmml.UsesMiscMode(Tegra::Shader::TextureMiscMode::NDV),
"NDV is not implemented");
@ -285,7 +287,6 @@ const Sampler& ShaderIR::GetSampler(const Tegra::Shader::Sampler& sampler, Textu
const Sampler& ShaderIR::GetBindlessSampler(const Tegra::Shader::Register& reg, TextureType type,
bool is_array, bool is_shadow) {
const Node sampler_register = GetRegister(reg);
const Node base_sampler =
TrackCbuf(sampler_register, global_code, static_cast<s64>(global_code.size()));

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@ -196,7 +196,7 @@ enum class ExitMethod {
class Sampler {
public:
// Use this constructor for binded Samplers
// Use this constructor for bounded Samplers
explicit Sampler(std::size_t offset, std::size_t index, Tegra::Shader::TextureType type,
bool is_array, bool is_shadow)
: offset{offset}, index{index}, type{type}, is_array{is_array}, is_shadow{is_shadow},
@ -239,7 +239,7 @@ public:
}
std::pair<u32, u32> GetBindlessCBuf() const {
return {offset >> 32, offset & 0x00000000FFFFFFFFULL};
return {static_cast<u32>(offset >> 32), static_cast<u32>(offset)};
}
bool operator<(const Sampler& rhs) const {