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https://github.com/yuzu-mirror/yuzu.git
synced 2024-09-07 06:39:08 +01:00
OpenGL: Implement Fencing backend.
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parent
ed7e965712
commit
487379c593
12 changed files with 94 additions and 19 deletions
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@ -397,14 +397,6 @@ void Maxwell3D::StampQueryResult(u64 payload, bool long_query) {
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}
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}
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void Maxwell3D::ReleaseFences() {
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for (const auto pair : delay_fences) {
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const auto [addr, payload] = pair;
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memory_manager.Write<u32>(addr, static_cast<u32>(payload));
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}
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delay_fences.clear();
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}
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void Maxwell3D::ProcessQueryGet() {
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// TODO(Subv): Support the other query units.
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ASSERT_MSG(regs.query.query_get.unit == Regs::QueryUnit::Crop,
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@ -412,10 +404,12 @@ void Maxwell3D::ProcessQueryGet() {
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switch (regs.query.query_get.operation) {
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case Regs::QueryOperation::Release: {
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rasterizer.FlushCommands();
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rasterizer.SyncGuestHost();
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const u64 result = regs.query.query_sequence;
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delay_fences.emplace_back(regs.query.QueryAddress(), result);
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if (regs.query.query_get.fence == 1) {
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rasterizer.SignalFence(regs.query.QueryAddress(), static_cast<u32>(result));
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} else {
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StampQueryResult(result, regs.query.query_get.short_query == 0);
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}
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break;
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}
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case Regs::QueryOperation::Acquire:
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@ -1427,8 +1427,6 @@ public:
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Tables tables{};
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} dirty;
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void ReleaseFences();
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private:
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void InitializeRegisterDefaults();
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@ -1469,8 +1467,6 @@ private:
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std::array<u8, Regs::NUM_REGS> dirty_pointers{};
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std::vector<std::pair<GPUVAddr, u64>> delay_fences;
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/// Retrieves information about a specific TIC entry from the TIC buffer.
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Texture::TICEntry GetTICEntry(u32 tic_index) const;
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@ -147,7 +147,7 @@ void GPU::SyncGuestHost() {
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}
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void GPU::OnCommandListEnd() {
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maxwell_3d->ReleaseFences();
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renderer.Rasterizer().ReleaseFences();
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}
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// Note that, traditionally, methods are treated as 4-byte addressable locations, and hence
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// their numbers are written down multiplied by 4 in Docs. Here we are not multiply by 4.
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@ -157,7 +157,7 @@ public:
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void FlushCommands();
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void SyncGuestHost();
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void OnCommandListEnd();
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virtual void OnCommandListEnd();
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/// Returns a reference to the Maxwell3D GPU engine.
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Engines::Maxwell3D& Maxwell3D();
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@ -52,4 +52,8 @@ void GPUAsynch::WaitIdle() const {
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gpu_thread.WaitIdle();
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}
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void GPUAsynch::OnCommandListEnd() {
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gpu_thread.OnCommandListEnd();
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}
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} // namespace VideoCommon
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@ -32,6 +32,8 @@ public:
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void FlushAndInvalidateRegion(VAddr addr, u64 size) override;
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void WaitIdle() const override;
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void OnCommandListEnd() override;
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protected:
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void TriggerCpuInterrupt(u32 syncpoint_id, u32 value) const override;
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@ -37,6 +37,8 @@ static void RunThread(VideoCore::RendererBase& renderer, Core::Frontend::Graphic
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dma_pusher.DispatchCalls();
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} else if (const auto data = std::get_if<SwapBuffersCommand>(&next.data)) {
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renderer.SwapBuffers(data->framebuffer ? &*data->framebuffer : nullptr);
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} else if (const auto data = std::get_if<OnCommandListEndCommand>(&next.data)) {
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renderer.Rasterizer().ReleaseFences();
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} else if (const auto data = std::get_if<FlushRegionCommand>(&next.data)) {
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renderer.Rasterizer().FlushRegion(data->addr, data->size);
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} else if (const auto data = std::get_if<InvalidateRegionCommand>(&next.data)) {
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@ -95,6 +97,10 @@ void ThreadManager::WaitIdle() const {
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}
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}
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void ThreadManager::OnCommandListEnd() {
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PushCommand(OnCommandListEndCommand());
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}
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u64 ThreadManager::PushCommand(CommandData&& command_data) {
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const u64 fence{++state.last_fence};
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state.queue.Push(CommandDataContainer(std::move(command_data), fence));
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@ -70,9 +70,12 @@ struct FlushAndInvalidateRegionCommand final {
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u64 size;
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};
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/// Command to signal to the GPU thread that processing has ended
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struct OnCommandListEndCommand final {};
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using CommandData =
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std::variant<EndProcessingCommand, SubmitListCommand, SwapBuffersCommand, FlushRegionCommand,
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InvalidateRegionCommand, FlushAndInvalidateRegionCommand>;
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InvalidateRegionCommand, FlushAndInvalidateRegionCommand, OnCommandListEndCommand>;
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struct CommandDataContainer {
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CommandDataContainer() = default;
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@ -122,6 +125,8 @@ public:
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// Wait until the gpu thread is idle.
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void WaitIdle() const;
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void OnCommandListEnd();
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private:
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/// Pushes a command to be executed by the GPU thread
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u64 PushCommand(CommandData&& command_data);
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@ -49,6 +49,14 @@ public:
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/// Records a GPU query and caches it
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virtual void Query(GPUVAddr gpu_addr, QueryType type, std::optional<u64> timestamp) = 0;
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virtual void SignalFence(GPUVAddr addr, u32 value) {
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}
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virtual void ReleaseFences() {
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}
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/// Notify rasterizer that all caches should be flushed to Switch memory
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virtual void FlushAll() = 0;
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@ -676,6 +676,34 @@ void RasterizerOpenGL::SyncGuestHost() {
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buffer_cache.SyncGuestHost();
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}
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void RasterizerOpenGL::SignalFence(GPUVAddr addr, u32 value) {
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if (!fences.empty()) {
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const std::pair<GPUVAddr, u32>& current_fence = fences.front();
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const auto [address, payload] = current_fence;
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texture_cache.PopAsyncFlushes();
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auto& gpu{system.GPU()};
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auto& memory_manager{gpu.MemoryManager()};
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memory_manager.Write<u32>(address, payload);
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fences.pop_front();
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}
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fences.emplace_back(addr, value);
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texture_cache.CommitAsyncFlushes();
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FlushCommands();
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SyncGuestHost();
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}
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void RasterizerOpenGL::ReleaseFences() {
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while (!fences.empty()) {
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const std::pair<GPUVAddr, u32>& current_fence = fences.front();
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const auto [address, payload] = current_fence;
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texture_cache.PopAsyncFlushes();
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auto& gpu{system.GPU()};
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auto& memory_manager{gpu.MemoryManager()};
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memory_manager.Write<u32>(address, payload);
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fences.pop_front();
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}
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}
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void RasterizerOpenGL::FlushAndInvalidateRegion(VAddr addr, u64 size) {
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if (Settings::IsGPULevelExtreme()) {
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FlushRegion(addr, size);
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@ -69,6 +69,8 @@ public:
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void InvalidateRegion(VAddr addr, u64 size) override;
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void OnCPUWrite(VAddr addr, u64 size) override;
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void SyncGuestHost() override;
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void SignalFence(GPUVAddr addr, u32 value) override;
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void ReleaseFences() override;
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void FlushAndInvalidateRegion(VAddr addr, u64 size) override;
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void FlushCommands() override;
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void TickFrame() override;
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@ -238,7 +238,7 @@ public:
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surface->MarkAsRenderTarget(false, NO_RT);
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const auto& cr_params = surface->GetSurfaceParams();
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if (!cr_params.is_tiled) {
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FlushSurface(surface);
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AsyncFlushSurface(surface);
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}
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}
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render_targets[index].target = surface_view.first;
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@ -317,6 +317,26 @@ public:
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return ++ticks;
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}
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void CommitAsyncFlushes() {
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commited_flushes.push_back(uncommited_flushes);
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uncommited_flushes.reset();
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}
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void PopAsyncFlushes() {
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if (commited_flushes.empty()) {
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return;
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}
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auto& flush_list = commited_flushes.front();
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if (!flush_list) {
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commited_flushes.pop_front();
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return;
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}
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for (TSurface& surface : *flush_list) {
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FlushSurface(surface);
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}
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commited_flushes.pop_front();
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}
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protected:
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explicit TextureCache(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
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bool is_astc_supported)
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@ -1152,6 +1172,13 @@ private:
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TView view;
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};
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void AsyncFlushSurface(TSurface& surface) {
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if (!uncommited_flushes) {
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uncommited_flushes = std::make_shared<std::list<TSurface>>();
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}
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uncommited_flushes->push_back(surface);
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}
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VideoCore::RasterizerInterface& rasterizer;
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FormatLookupTable format_lookup_table;
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@ -1198,6 +1225,9 @@ private:
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std::list<TSurface> marked_for_unregister;
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std::shared_ptr<std::list<TSurface>> uncommited_flushes{};
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std::list<std::shared_ptr<std::list<TSurface>>> commited_flushes;
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StagingCache staging_cache;
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std::recursive_mutex mutex;
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};
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