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shader/other: Implement MEMBAR.CTS
This silences an assertion we were hitting and uses workgroup memory barriers when the game requests it.
This commit is contained in:
parent
508242c267
commit
32e6727dae
4 changed files with 27 additions and 9 deletions
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@ -2344,7 +2344,12 @@ private:
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return {};
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return {};
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}
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}
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Expression MemoryBarrierGL(Operation) {
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Expression MemoryBarrierGroup(Operation) {
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code.AddLine("groupMemoryBarrier();");
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return {};
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}
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Expression MemoryBarrierGlobal(Operation) {
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code.AddLine("memoryBarrier();");
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code.AddLine("memoryBarrier();");
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return {};
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return {};
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}
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}
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@ -2591,7 +2596,8 @@ private:
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&GLSLDecompiler::ShuffleIndexed,
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&GLSLDecompiler::ShuffleIndexed,
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&GLSLDecompiler::Barrier,
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&GLSLDecompiler::Barrier,
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&GLSLDecompiler::MemoryBarrierGL,
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&GLSLDecompiler::MemoryBarrierGroup,
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&GLSLDecompiler::MemoryBarrierGlobal,
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};
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};
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static_assert(operation_decompilers.size() == static_cast<std::size_t>(OperationCode::Amount));
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static_assert(operation_decompilers.size() == static_cast<std::size_t>(OperationCode::Amount));
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@ -2215,8 +2215,8 @@ private:
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return {};
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return {};
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}
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}
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Expression MemoryBarrierGL(Operation) {
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template <spv::Scope scope>
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const auto scope = spv::Scope::Device;
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Expression MemoryBarrier(Operation) {
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const auto semantics =
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const auto semantics =
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spv::MemorySemanticsMask::AcquireRelease | spv::MemorySemanticsMask::UniformMemory |
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spv::MemorySemanticsMask::AcquireRelease | spv::MemorySemanticsMask::UniformMemory |
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spv::MemorySemanticsMask::WorkgroupMemory |
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spv::MemorySemanticsMask::WorkgroupMemory |
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@ -2681,7 +2681,8 @@ private:
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&SPIRVDecompiler::ShuffleIndexed,
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&SPIRVDecompiler::ShuffleIndexed,
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&SPIRVDecompiler::Barrier,
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&SPIRVDecompiler::Barrier,
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&SPIRVDecompiler::MemoryBarrierGL,
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&SPIRVDecompiler::MemoryBarrier<spv::Scope::Workgroup>,
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&SPIRVDecompiler::MemoryBarrier<spv::Scope::Device>,
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};
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};
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static_assert(operation_decompilers.size() == static_cast<std::size_t>(OperationCode::Amount));
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static_assert(operation_decompilers.size() == static_cast<std::size_t>(OperationCode::Amount));
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@ -299,9 +299,19 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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break;
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break;
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}
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}
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case OpCode::Id::MEMBAR: {
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case OpCode::Id::MEMBAR: {
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UNIMPLEMENTED_IF(instr.membar.type != Tegra::Shader::MembarType::GL);
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UNIMPLEMENTED_IF(instr.membar.unknown != Tegra::Shader::MembarUnknown::Default);
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UNIMPLEMENTED_IF(instr.membar.unknown != Tegra::Shader::MembarUnknown::Default);
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bb.push_back(Operation(OperationCode::MemoryBarrierGL));
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const OperationCode type = [instr] {
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switch (instr.membar.type) {
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case Tegra::Shader::MembarType::CTA:
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return OperationCode::MemoryBarrierGroup;
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case Tegra::Shader::MembarType::GL:
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return OperationCode::MemoryBarrierGlobal;
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default:
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UNIMPLEMENTED_MSG("MEMBAR type={}", static_cast<int>(instr.membar.type.Value()));
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return OperationCode::MemoryBarrierGlobal;
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}
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}();
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bb.push_back(Operation(type));
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break;
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break;
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}
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}
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case OpCode::Id::DEPBAR: {
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case OpCode::Id::DEPBAR: {
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@ -233,8 +233,9 @@ enum class OperationCode {
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ThreadLtMask, /// () -> uint
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ThreadLtMask, /// () -> uint
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ShuffleIndexed, /// (uint value, uint index) -> uint
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ShuffleIndexed, /// (uint value, uint index) -> uint
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Barrier, /// () -> void
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Barrier, /// () -> void
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MemoryBarrierGL, /// () -> void
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MemoryBarrierGroup, /// () -> void
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MemoryBarrierGlobal, /// () -> void
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Amount,
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Amount,
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};
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};
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