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video_core: Implement maxwell inline_index method
This commit is contained in:
parent
1f54cd4ac7
commit
2f90694797
6 changed files with 135 additions and 79 deletions
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@ -126,6 +126,9 @@ void Maxwell3D::InitializeRegisterDefaults() {
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draw_command[MAXWELL3D_REG_INDEX(index_buffer32_first)] = true;
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draw_command[MAXWELL3D_REG_INDEX(index_buffer32_first)] = true;
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draw_command[MAXWELL3D_REG_INDEX(index_buffer16_first)] = true;
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draw_command[MAXWELL3D_REG_INDEX(index_buffer16_first)] = true;
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draw_command[MAXWELL3D_REG_INDEX(index_buffer8_first)] = true;
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draw_command[MAXWELL3D_REG_INDEX(index_buffer8_first)] = true;
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draw_command[MAXWELL3D_REG_INDEX(draw_inline_index)] = true;
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draw_command[MAXWELL3D_REG_INDEX(inline_index_2x16.even)] = true;
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draw_command[MAXWELL3D_REG_INDEX(inline_index_4x8.index0)] = true;
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}
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}
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void Maxwell3D::ProcessMacro(u32 method, const u32* base_start, u32 amount, bool is_last_call) {
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void Maxwell3D::ProcessMacro(u32 method, const u32* base_start, u32 amount, bool is_last_call) {
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@ -271,6 +274,23 @@ void Maxwell3D::CallMethod(u32 method, u32 method_argument, bool is_last_call) {
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if (draw_command[method]) {
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if (draw_command[method]) {
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regs.reg_array[method] = method_argument;
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regs.reg_array[method] = method_argument;
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deferred_draw_method.push_back(method);
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deferred_draw_method.push_back(method);
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auto u32_to_u8 = [&](const u32 argument) {
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inline_index_draw_indexes.push_back(static_cast<u8>(argument & 0x000000ff));
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inline_index_draw_indexes.push_back(static_cast<u8>((argument & 0x0000ff00) >> 8));
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inline_index_draw_indexes.push_back(static_cast<u8>((argument & 0x00ff0000) >> 16));
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inline_index_draw_indexes.push_back(static_cast<u8>((argument & 0xff000000) >> 24));
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};
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if (MAXWELL3D_REG_INDEX(draw_inline_index) == method) {
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u32_to_u8(method_argument);
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} else if (MAXWELL3D_REG_INDEX(inline_index_2x16.even) == method) {
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u32_to_u8(regs.inline_index_2x16.even);
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u32_to_u8(regs.inline_index_2x16.odd);
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} else if (MAXWELL3D_REG_INDEX(inline_index_4x8.index0) == method) {
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u32_to_u8(regs.inline_index_4x8.index0);
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u32_to_u8(regs.inline_index_4x8.index1);
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u32_to_u8(regs.inline_index_4x8.index2);
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u32_to_u8(regs.inline_index_4x8.index3);
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}
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} else {
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} else {
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ProcessDeferredDraw();
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ProcessDeferredDraw();
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@ -567,86 +587,94 @@ void Maxwell3D::ProcessClearBuffers() {
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}
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}
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void Maxwell3D::ProcessDeferredDraw() {
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void Maxwell3D::ProcessDeferredDraw() {
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auto method_count = deferred_draw_method.size();
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if (deferred_draw_method.empty()) {
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if (method_count) {
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return;
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enum class DrawMode {
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}
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Undefined,
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General,
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Instance,
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};
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DrawMode draw_mode{DrawMode::Undefined};
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u32 instance_count = 1;
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auto first_method = deferred_draw_method[0];
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enum class DrawMode {
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if (MAXWELL3D_REG_INDEX(draw.begin) == first_method) {
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Undefined,
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// The minimum number of methods for drawing must be greater than or equal to
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General,
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// 3[draw.begin->vertex(index)count->draw.end] to avoid errors in index mode drawing
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Instance,
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if (method_count < 3) {
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};
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return;
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DrawMode draw_mode{DrawMode::Undefined};
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}
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u32 instance_count = 1;
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draw_mode =
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(regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::Subsequent) ||
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(regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::Unchanged)
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? DrawMode::Instance
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: DrawMode::General;
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} else if (MAXWELL3D_REG_INDEX(index_buffer32_first) == first_method ||
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MAXWELL3D_REG_INDEX(index_buffer16_first) == first_method ||
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MAXWELL3D_REG_INDEX(index_buffer8_first) == first_method) {
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draw_mode = DrawMode::General;
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}
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// Drawing will only begin with draw.begin or index_buffer method, other methods directly
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auto first_method = deferred_draw_method[0];
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// clear
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if (MAXWELL3D_REG_INDEX(draw.begin) == first_method) {
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if (draw_mode == DrawMode::Undefined) {
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// The minimum number of methods for drawing must be greater than or equal to
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deferred_draw_method.clear();
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// 3[draw.begin->vertex(index)count->draw.end] to avoid errors in index mode drawing
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if (deferred_draw_method.size() < 3) {
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return;
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return;
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}
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}
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draw_mode = (regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::Subsequent) ||
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(regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::Unchanged)
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? DrawMode::Instance
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: DrawMode::General;
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} else if (MAXWELL3D_REG_INDEX(index_buffer32_first) == first_method ||
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MAXWELL3D_REG_INDEX(index_buffer16_first) == first_method ||
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MAXWELL3D_REG_INDEX(index_buffer8_first) == first_method) {
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draw_mode = DrawMode::General;
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}
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if (draw_mode == DrawMode::Instance) {
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// Drawing will only begin with draw.begin or index_buffer method, other methods directly
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ASSERT_MSG(deferred_draw_method.size() % 4 == 0, "Instance mode method size error");
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// clear
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instance_count = static_cast<u32>(deferred_draw_method.size()) / 4;
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if (draw_mode == DrawMode::Undefined) {
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deferred_draw_method.clear();
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return;
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}
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if (draw_mode == DrawMode::Instance) {
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ASSERT_MSG(deferred_draw_method.size() % 4 == 0, "Instance mode method size error");
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instance_count = static_cast<u32>(deferred_draw_method.size()) / 4;
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} else {
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if (MAXWELL3D_REG_INDEX(index_buffer32_first) == first_method) {
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regs.index_buffer.count = regs.index_buffer32_first.count;
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regs.index_buffer.first = regs.index_buffer32_first.first;
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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} else if (MAXWELL3D_REG_INDEX(index_buffer32_first) == first_method) {
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regs.index_buffer.count = regs.index_buffer16_first.count;
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regs.index_buffer.first = regs.index_buffer16_first.first;
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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} else if (MAXWELL3D_REG_INDEX(index_buffer32_first) == first_method) {
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regs.index_buffer.count = regs.index_buffer8_first.count;
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regs.index_buffer.first = regs.index_buffer8_first.first;
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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} else {
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} else {
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if (MAXWELL3D_REG_INDEX(index_buffer32_first) == first_method) {
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auto second_method = deferred_draw_method[1];
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regs.index_buffer.count = regs.index_buffer32_first.count;
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if (MAXWELL3D_REG_INDEX(draw_inline_index) == second_method ||
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regs.index_buffer.first = regs.index_buffer32_first.first;
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MAXWELL3D_REG_INDEX(inline_index_2x16.even) == second_method ||
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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MAXWELL3D_REG_INDEX(inline_index_4x8.index0) == second_method) {
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} else if (MAXWELL3D_REG_INDEX(index_buffer32_first) == first_method) {
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regs.index_buffer.count = static_cast<u32>(inline_index_draw_indexes.size() / 4);
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regs.index_buffer.count = regs.index_buffer16_first.count;
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regs.index_buffer.format = Regs::IndexFormat::UnsignedInt;
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regs.index_buffer.first = regs.index_buffer16_first.first;
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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} else if (MAXWELL3D_REG_INDEX(index_buffer32_first) == first_method) {
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regs.index_buffer.count = regs.index_buffer8_first.count;
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regs.index_buffer.first = regs.index_buffer8_first.first;
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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}
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}
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}
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}
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LOG_TRACE(HW_GPU, "called, topology={}, count={}", regs.draw.topology.Value(),
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regs.vertex_buffer.count);
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ASSERT_MSG(!(regs.index_buffer.count && regs.vertex_buffer.count),
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"Both indexed and direct?");
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// Both instance configuration registers can not be set at the same time.
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ASSERT_MSG(regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::First ||
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regs.draw.instance_id != Maxwell3D::Regs::Draw::InstanceId::Unchanged,
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"Illegal combination of instancing parameters");
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ProcessTopologyOverride();
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const bool is_indexed = regs.index_buffer.count && !regs.vertex_buffer.count;
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if (ShouldExecute()) {
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rasterizer->Draw(is_indexed, instance_count);
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}
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if (is_indexed) {
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regs.index_buffer.count = 0;
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} else {
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regs.vertex_buffer.count = 0;
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}
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deferred_draw_method.clear();
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}
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}
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LOG_TRACE(HW_GPU, "called, topology={}, count={}", regs.draw.topology.Value(),
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regs.vertex_buffer.count);
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ASSERT_MSG(!(regs.index_buffer.count && regs.vertex_buffer.count), "Both indexed and direct?");
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// Both instance configuration registers can not be set at the same time.
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ASSERT_MSG(regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::First ||
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regs.draw.instance_id != Maxwell3D::Regs::Draw::InstanceId::Unchanged,
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"Illegal combination of instancing parameters");
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ProcessTopologyOverride();
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const bool is_indexed = regs.index_buffer.count && !regs.vertex_buffer.count;
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if (ShouldExecute()) {
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rasterizer->Draw(is_indexed, instance_count);
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}
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if (is_indexed) {
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regs.index_buffer.count = 0;
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} else {
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regs.vertex_buffer.count = 0;
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}
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deferred_draw_method.clear();
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inline_index_draw_indexes.clear();
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}
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}
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} // namespace Tegra::Engines
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} // namespace Tegra::Engines
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@ -1739,14 +1739,11 @@ public:
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Footprint_1x1_Virtual = 2,
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Footprint_1x1_Virtual = 2,
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};
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};
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struct InlineIndex4x8Align {
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struct InlineIndex4x8 {
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union {
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union {
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BitField<0, 30, u32> count;
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BitField<0, 30, u32> count;
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BitField<30, 2, u32> start;
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BitField<30, 2, u32> start;
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};
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};
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};
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struct InlineIndex4x8Index {
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union {
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union {
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BitField<0, 8, u32> index0;
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BitField<0, 8, u32> index0;
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BitField<8, 8, u32> index1;
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BitField<8, 8, u32> index1;
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@ -2836,8 +2833,7 @@ public:
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u32 depth_write_enabled; ///< 0x12E8
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u32 depth_write_enabled; ///< 0x12E8
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u32 alpha_test_enabled; ///< 0x12EC
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u32 alpha_test_enabled; ///< 0x12EC
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INSERT_PADDING_BYTES_NOINIT(0x10);
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INSERT_PADDING_BYTES_NOINIT(0x10);
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InlineIndex4x8Align inline_index_4x8_align; ///< 0x1300
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InlineIndex4x8 inline_index_4x8; ///< 0x1300
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InlineIndex4x8Index inline_index_4x8_index; ///< 0x1304
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D3DCullMode d3d_cull_mode; ///< 0x1308
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D3DCullMode d3d_cull_mode; ///< 0x1308
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ComparisonOp depth_test_func; ///< 0x130C
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ComparisonOp depth_test_func; ///< 0x130C
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f32 alpha_test_ref; ///< 0x1310
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f32 alpha_test_ref; ///< 0x1310
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@ -3083,6 +3079,8 @@ public:
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Tables tables{};
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Tables tables{};
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} dirty;
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} dirty;
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std::vector<u8> inline_index_draw_indexes;
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private:
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private:
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void InitializeRegisterDefaults();
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void InitializeRegisterDefaults();
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@ -3377,8 +3375,7 @@ ASSERT_REG_POSITION(alpha_to_coverage_dither, 0x12E0);
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ASSERT_REG_POSITION(blend_per_target_enabled, 0x12E4);
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ASSERT_REG_POSITION(blend_per_target_enabled, 0x12E4);
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ASSERT_REG_POSITION(depth_write_enabled, 0x12E8);
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ASSERT_REG_POSITION(depth_write_enabled, 0x12E8);
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ASSERT_REG_POSITION(alpha_test_enabled, 0x12EC);
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ASSERT_REG_POSITION(alpha_test_enabled, 0x12EC);
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ASSERT_REG_POSITION(inline_index_4x8_align, 0x1300);
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ASSERT_REG_POSITION(inline_index_4x8, 0x1300);
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ASSERT_REG_POSITION(inline_index_4x8_index, 0x1304);
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ASSERT_REG_POSITION(d3d_cull_mode, 0x1308);
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ASSERT_REG_POSITION(d3d_cull_mode, 0x1308);
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ASSERT_REG_POSITION(depth_test_func, 0x130C);
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ASSERT_REG_POSITION(depth_test_func, 0x130C);
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ASSERT_REG_POSITION(alpha_test_ref, 0x1310);
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ASSERT_REG_POSITION(alpha_test_ref, 0x1310);
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@ -222,6 +222,8 @@ void RasterizerOpenGL::Draw(bool is_indexed, u32 instance_count) {
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pipeline->SetEngine(maxwell3d, gpu_memory);
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pipeline->SetEngine(maxwell3d, gpu_memory);
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pipeline->Configure(is_indexed);
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pipeline->Configure(is_indexed);
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BindInlineIndexBuffer();
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SyncState();
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SyncState();
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const GLenum primitive_mode = MaxwellToGL::PrimitiveTopology(maxwell3d->regs.draw.topology);
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const GLenum primitive_mode = MaxwellToGL::PrimitiveTopology(maxwell3d->regs.draw.topology);
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@ -1128,6 +1130,16 @@ void RasterizerOpenGL::ReleaseChannel(s32 channel_id) {
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query_cache.EraseChannel(channel_id);
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query_cache.EraseChannel(channel_id);
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}
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}
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void RasterizerOpenGL::BindInlineIndexBuffer() {
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if (maxwell3d->inline_index_draw_indexes.empty()) {
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return;
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}
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const auto data_count = static_cast<u32>(maxwell3d->inline_index_draw_indexes.size());
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auto buffer = Buffer(buffer_cache_runtime, *this, 0, data_count);
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buffer.ImmediateUpload(0, maxwell3d->inline_index_draw_indexes);
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buffer_cache_runtime.BindIndexBuffer(buffer, 0, data_count);
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}
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AccelerateDMA::AccelerateDMA(BufferCache& buffer_cache_) : buffer_cache{buffer_cache_} {}
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AccelerateDMA::AccelerateDMA(BufferCache& buffer_cache_) : buffer_cache{buffer_cache_} {}
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bool AccelerateDMA::BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) {
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bool AccelerateDMA::BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) {
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/// End a transform feedback
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/// End a transform feedback
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void EndTransformFeedback();
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void EndTransformFeedback();
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void BindInlineIndexBuffer();
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Tegra::GPU& gpu;
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Tegra::GPU& gpu;
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const Device& device;
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const Device& device;
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@ -193,6 +193,8 @@ void RasterizerVulkan::Draw(bool is_indexed, u32 instance_count) {
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pipeline->SetEngine(maxwell3d, gpu_memory);
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pipeline->SetEngine(maxwell3d, gpu_memory);
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pipeline->Configure(is_indexed);
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pipeline->Configure(is_indexed);
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BindInlineIndexBuffer();
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BeginTransformFeedback();
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BeginTransformFeedback();
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UpdateDynamicStates();
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UpdateDynamicStates();
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@ -1008,4 +1010,17 @@ void RasterizerVulkan::ReleaseChannel(s32 channel_id) {
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query_cache.EraseChannel(channel_id);
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query_cache.EraseChannel(channel_id);
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}
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}
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void RasterizerVulkan::BindInlineIndexBuffer() {
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if (maxwell3d->inline_index_draw_indexes.empty()) {
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return;
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}
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const auto data_count = static_cast<u32>(maxwell3d->inline_index_draw_indexes.size());
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auto buffer = buffer_cache_runtime.UploadStagingBuffer(data_count);
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std::memcpy(buffer.mapped_span.data(), maxwell3d->inline_index_draw_indexes.data(), data_count);
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buffer_cache_runtime.BindIndexBuffer(
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maxwell3d->regs.draw.topology, maxwell3d->regs.index_buffer.format,
|
||||||
|
maxwell3d->regs.index_buffer.first, maxwell3d->regs.index_buffer.count, buffer.buffer,
|
||||||
|
static_cast<u32>(buffer.offset), data_count);
|
||||||
|
}
|
||||||
|
|
||||||
} // namespace Vulkan
|
} // namespace Vulkan
|
||||||
|
|
|
@ -141,6 +141,8 @@ private:
|
||||||
|
|
||||||
void UpdateVertexInput(Tegra::Engines::Maxwell3D::Regs& regs);
|
void UpdateVertexInput(Tegra::Engines::Maxwell3D::Regs& regs);
|
||||||
|
|
||||||
|
void BindInlineIndexBuffer();
|
||||||
|
|
||||||
Tegra::GPU& gpu;
|
Tegra::GPU& gpu;
|
||||||
|
|
||||||
ScreenInfo& screen_info;
|
ScreenInfo& screen_info;
|
||||||
|
|
Loading…
Reference in a new issue