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Shaders: Corrected the 'abs' and 'neg' bit usage in the float arithmetic instructions.
We should definitely audit our shader generator for more errors like this.
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24a759de4a
commit
2e95ba2e9c
2 changed files with 38 additions and 16 deletions
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@ -282,6 +282,10 @@ union Instruction {
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}
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} alu;
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union {
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BitField<48, 1, u64> negate_b;
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} fmul;
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union {
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BitField<48, 1, u64> is_signed;
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} shift;
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@ -741,6 +741,30 @@ private:
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return op->second;
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}
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/**
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* Transforms the input string GLSL operand into one that applies the abs() function and negates
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* the output if necessary. When both abs and neg are true, the negation will be applied after
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* taking the absolute value.
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* @param operand The input operand to take the abs() of, negate, or both.
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* @param abs Whether to apply the abs() function to the input operand.
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* @param neg Whether to negate the input operand.
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* @returns String corresponding to the operand after being transformed by the abs() and
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* negation operations.
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*/
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static std::string GetOperandAbsNeg(const std::string& operand, bool abs, bool neg) {
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std::string result = operand;
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if (abs) {
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result = "abs(" + result + ')';
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}
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if (neg) {
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result = "-(" + result + ')';
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}
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return result;
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}
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/*
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* Returns whether the instruction at the specified offset is a 'sched' instruction.
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* Sched instructions always appear before a sequence of 3 instructions.
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@ -857,13 +881,6 @@ private:
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switch (opcode->GetType()) {
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case OpCode::Type::Arithmetic: {
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std::string op_a = regs.GetRegisterAsFloat(instr.gpr8);
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if (instr.alu.abs_a) {
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op_a = "abs(" + op_a + ')';
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}
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if (instr.alu.negate_a) {
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op_a = "-(" + op_a + ')';
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}
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std::string op_b;
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@ -878,17 +895,10 @@ private:
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}
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}
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if (instr.alu.abs_b) {
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op_b = "abs(" + op_b + ')';
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}
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if (instr.alu.negate_b) {
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op_b = "-(" + op_b + ')';
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}
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switch (opcode->GetId()) {
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case OpCode::Id::MOV_C:
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case OpCode::Id::MOV_R: {
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// MOV does not have neither 'abs' nor 'neg' bits.
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regs.SetRegisterToFloat(instr.gpr0, 0, op_b, 1, 1);
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break;
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}
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@ -896,6 +906,8 @@ private:
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case OpCode::Id::FMUL_C:
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case OpCode::Id::FMUL_R:
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case OpCode::Id::FMUL_IMM: {
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// FMUL does not have 'abs' bits and only the second operand has a 'neg' bit.
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op_b = GetOperandAbsNeg(op_b, false, instr.fmul.negate_b);
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1,
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instr.alu.saturate_d);
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break;
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@ -903,11 +915,14 @@ private:
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case OpCode::Id::FADD_C:
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case OpCode::Id::FADD_R:
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case OpCode::Id::FADD_IMM: {
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op_a = GetOperandAbsNeg(op_a, instr.alu.abs_a, instr.alu.negate_a);
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op_b = GetOperandAbsNeg(op_b, instr.alu.abs_b, instr.alu.negate_b);
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " + " + op_b, 1, 1,
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instr.alu.saturate_d);
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break;
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}
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case OpCode::Id::MUFU: {
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op_a = GetOperandAbsNeg(op_a, instr.alu.abs_a, instr.alu.negate_a);
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switch (instr.sub_op) {
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case SubOp::Cos:
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regs.SetRegisterToFloat(instr.gpr0, 0, "cos(" + op_a + ')', 1, 1,
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@ -947,6 +962,9 @@ private:
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case OpCode::Id::FMNMX_C:
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case OpCode::Id::FMNMX_R:
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case OpCode::Id::FMNMX_IMM: {
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op_a = GetOperandAbsNeg(op_a, instr.alu.abs_a, instr.alu.negate_a);
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op_b = GetOperandAbsNeg(op_b, instr.alu.abs_b, instr.alu.negate_b);
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std::string condition =
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GetPredicateCondition(instr.alu.fmnmx.pred, instr.alu.fmnmx.negate_pred != 0);
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std::string parameters = op_a + ',' + op_b;
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@ -960,7 +978,7 @@ private:
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case OpCode::Id::RRO_R:
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case OpCode::Id::RRO_IMM: {
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// Currently RRO is only implemented as a register move.
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// Usage of `abs_b` and `negate_b` here should also be correct.
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op_b = GetOperandAbsNeg(op_b, instr.alu.abs_b, instr.alu.negate_b);
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regs.SetRegisterToFloat(instr.gpr0, 0, op_b, 1, 1);
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LOG_WARNING(HW_GPU, "RRO instruction is incomplete");
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break;
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