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Shader_Ir: Fix TLD4S from using a component mask.
TLD4S always outputs 4 values, the previous code checked a component mask and omitted those values that weren't part of it. This commit corrects that and makes sure all 4 values are set.
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parent
1572fb9bf2
commit
1509d2ffbd
2 changed files with 5 additions and 5 deletions
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@ -150,7 +150,7 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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values[element] = Operation(OperationCode::TextureGather, meta, std::move(coords_copy));
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}
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WriteTexsInstructionFloat(bb, instr, values);
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WriteTexsInstructionFloat(bb, instr, values, true);
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break;
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}
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case OpCode::Id::TXQ_B:
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@ -344,14 +344,14 @@ void ShaderIR::WriteTexInstructionFloat(NodeBlock& bb, Instruction instr, const
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}
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}
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void ShaderIR::WriteTexsInstructionFloat(NodeBlock& bb, Instruction instr,
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const Node4& components) {
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void ShaderIR::WriteTexsInstructionFloat(NodeBlock& bb, Instruction instr, const Node4& components,
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bool ignore_mask) {
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// TEXS has two destination registers and a swizzle. The first two elements in the swizzle
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// go into gpr0+0 and gpr0+1, and the rest goes into gpr28+0 and gpr28+1
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u32 dest_elem = 0;
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for (u32 component = 0; component < 4; ++component) {
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if (!instr.texs.IsComponentEnabled(component))
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if (!instr.texs.IsComponentEnabled(component) && !ignore_mask)
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continue;
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SetTemporary(bb, dest_elem++, components[component]);
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}
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@ -322,7 +322,7 @@ private:
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const Node4& components);
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void WriteTexsInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
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const Node4& components);
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const Node4& components, bool ignore_mask = false);
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void WriteTexsInstructionHalfFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
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const Node4& components);
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