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Pica: Implement command buffer execution registers.
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parent
4ac6c1a3b5
commit
02c9fe202c
2 changed files with 75 additions and 43 deletions
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@ -56,7 +56,17 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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// Trigger IRQ
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case PICA_REG_INDEX(trigger_irq):
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::P3D);
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return;
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break;
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case PICA_REG_INDEX_WORKAROUND(command_buffer.trigger[0], 0x23c):
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case PICA_REG_INDEX_WORKAROUND(command_buffer.trigger[1], 0x23d):
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{
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unsigned index = id - PICA_REG_INDEX(command_buffer.trigger[0]);
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u32* head_ptr = (u32*)Memory::GetPhysicalPointer(regs.command_buffer.GetPhysicalAddress(index));
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g_state.cmd_list.head_ptr = g_state.cmd_list.current_ptr = head_ptr;
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g_state.cmd_list.length = regs.command_buffer.GetSize(index) / sizeof(u32);
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break;
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}
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// It seems like these trigger vertex rendering
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case PICA_REG_INDEX(trigger_draw):
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@ -363,38 +373,34 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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g_debug_context->OnEvent(DebugContext::Event::CommandProcessed, reinterpret_cast<void*>(&id));
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}
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static std::ptrdiff_t ExecuteCommandBlock(const u32* first_command_word) {
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const CommandHeader& header = *(const CommandHeader*)(&first_command_word[1]);
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u32* read_pointer = (u32*)first_command_word;
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const u32 write_mask = ((header.parameter_mask & 0x1) ? (0xFFu << 0) : 0u) |
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((header.parameter_mask & 0x2) ? (0xFFu << 8) : 0u) |
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((header.parameter_mask & 0x4) ? (0xFFu << 16) : 0u) |
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((header.parameter_mask & 0x8) ? (0xFFu << 24) : 0u);
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WritePicaReg(header.cmd_id, *read_pointer, write_mask);
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read_pointer += 2;
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for (unsigned int i = 1; i < 1+header.extra_data_length; ++i) {
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u32 cmd = header.cmd_id + ((header.group_commands) ? i : 0);
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WritePicaReg(cmd, *read_pointer, write_mask);
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++read_pointer;
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}
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// align read pointer to 8 bytes
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if ((first_command_word - read_pointer) % 2)
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++read_pointer;
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return read_pointer - first_command_word;
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}
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void ProcessCommandList(const u32* list, u32 size) {
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u32* read_pointer = (u32*)list;
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u32 list_length = size / sizeof(u32);
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g_state.cmd_list.head_ptr = g_state.cmd_list.current_ptr = list;
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g_state.cmd_list.length = size / sizeof(u32);
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while (read_pointer < list + list_length) {
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read_pointer += ExecuteCommandBlock(read_pointer);
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while (g_state.cmd_list.current_ptr < g_state.cmd_list.head_ptr + g_state.cmd_list.length) {
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// Expand a 4-bit mask to 4-byte mask, e.g. 0b0101 -> 0x00FF00FF
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static const u32 expand_bits_to_bytes[] = {
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0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff,
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0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
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0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff,
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0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff
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};
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// Align read pointer to 8 bytes
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if ((g_state.cmd_list.head_ptr - g_state.cmd_list.current_ptr) % 2 != 0)
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++g_state.cmd_list.current_ptr;
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u32 value = *g_state.cmd_list.current_ptr++;
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const CommandHeader header = { *g_state.cmd_list.current_ptr++ };
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const u32 write_mask = expand_bits_to_bytes[header.parameter_mask];
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u32 cmd = header.cmd_id;
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WritePicaReg(cmd, value, write_mask);
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for (unsigned i = 0; i < header.extra_data_length; ++i) {
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u32 cmd = header.cmd_id + (header.group_commands ? i + 1 : 0);
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WritePicaReg(cmd, *g_state.cmd_list.current_ptr++, write_mask);
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}
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}
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}
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@ -708,7 +708,33 @@ struct Regs {
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u32 set_value[3];
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} vs_default_attributes_setup;
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INSERT_PADDING_WORDS(0x28);
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INSERT_PADDING_WORDS(0x2);
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struct {
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// There are two channels that can be used to configure the next command buffer, which
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// can be then executed by writing to the "trigger" registers. There are two reasons why a
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// game might use this feature:
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// 1) With this, an arbitrary number of additional command buffers may be executed in
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// sequence without requiring any intervention of the CPU after the initial one is
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// kicked off.
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// 2) Games can configure these registers to provide a command list subroutine mechanism.
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BitField< 0, 20, u32> size[2]; ///< Size (in bytes / 8) of each channel's command buffer
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BitField< 0, 28, u32> addr[2]; ///< Physical address / 8 of each channel's command buffer
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u32 trigger[2]; ///< Triggers execution of the channel's command buffer when written to
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unsigned GetSize(unsigned index) const {
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ASSERT(index < 2);
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return 8 * size[index];
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}
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PAddr GetPhysicalAddress(unsigned index) const {
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ASSERT(index < 2);
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return (PAddr)(8 * addr[index]);
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}
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} command_buffer;
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INSERT_PADDING_WORDS(0x20);
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enum class TriangleTopology : u32 {
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List = 0,
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@ -861,6 +887,7 @@ struct Regs {
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ADD_FIELD(trigger_draw);
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ADD_FIELD(trigger_draw_indexed);
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ADD_FIELD(vs_default_attributes_setup);
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ADD_FIELD(command_buffer);
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ADD_FIELD(triangle_topology);
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ADD_FIELD(vs_bool_uniforms);
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ADD_FIELD(vs_int_uniforms);
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@ -938,6 +965,7 @@ ASSERT_REG_POSITION(num_vertices, 0x228);
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ASSERT_REG_POSITION(trigger_draw, 0x22e);
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ASSERT_REG_POSITION(trigger_draw_indexed, 0x22f);
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ASSERT_REG_POSITION(vs_default_attributes_setup, 0x232);
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ASSERT_REG_POSITION(command_buffer, 0x238);
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ASSERT_REG_POSITION(triangle_topology, 0x25e);
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ASSERT_REG_POSITION(vs_bool_uniforms, 0x2b0);
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ASSERT_REG_POSITION(vs_int_uniforms, 0x2b1);
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@ -1053,21 +1081,12 @@ private:
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float value;
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};
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union CommandHeader {
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CommandHeader(u32 h) : hex(h) {}
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u32 hex;
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BitField< 0, 16, u32> cmd_id;
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BitField<16, 4, u32> parameter_mask;
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BitField<20, 11, u32> extra_data_length;
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BitField<31, 1, u32> group_commands;
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};
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/// Struct used to describe current Pica state
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struct State {
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/// Pica registers
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Regs regs;
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/// Vertex shader memory
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struct {
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struct {
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Math::Vec4<float24> f[96];
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@ -1080,6 +1099,13 @@ struct State {
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std::array<u32, 1024> program_code;
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std::array<u32, 1024> swizzle_data;
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} vs;
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/// Current Pica command list
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struct {
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const u32* head_ptr;
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const u32* current_ptr;
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u32 length;
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} cmd_list;
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};
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/// Initialize Pica state
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