Valentin PONS 3af2ce74ec Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192) ... * Added some 32 bits instructions: * VBIC * VTST * VSRA * Incremented the PTC * Add tests and fix implementation * Fixed VBIC immediate opcode mapping * Hey hey! * Nit. Co-authored-by: gdkchan <gab.dark.100@gmail.com> Co-authored-by: LDj3SNuD <dvitiello@gmail.com> Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>		2020-07-19 15:11:58 -03:00
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Optimizations
Block.cs
Condition.cs
DataOp.cs
Decoder.cs
DecoderHelper.cs
InstDescriptor.cs
InstEmitter.cs
IntType.cs
IOpCode.cs
IOpCode32.cs
IOpCode32Alu.cs
IOpCode32AluBf.cs
IOpCode32AluReg.cs
IOpCode32AluUx.cs
IOpCode32BImm.cs
IOpCode32BReg.cs
IOpCode32Mem.cs
IOpCode32MemEx.cs
IOpCode32MemMult.cs
IOpCode32Simd.cs
IOpCode32SimdImm.cs
IOpCodeAlu.cs
IOpCodeAluImm.cs
IOpCodeAluRs.cs
IOpCodeAluRx.cs
IOpCodeBImm.cs
IOpCodeCond.cs
IOpCodeLit.cs
IOpCodeSimd.cs
OpCode.cs
OpCode32.cs
OpCode32Alu.cs
OpCode32AluBf.cs
OpCode32AluImm.cs
OpCode32AluImm16.cs
OpCode32AluMla.cs
OpCode32AluReg.cs
OpCode32AluRsImm.cs
OpCode32AluRsReg.cs
OpCode32AluUmull.cs
OpCode32AluUx.cs
OpCode32BImm.cs
OpCode32BReg.cs
OpCode32Exception.cs
OpCode32Mem.cs
OpCode32MemImm.cs
OpCode32MemImm8.cs
OpCode32MemLdEx.cs
OpCode32MemMult.cs
OpCode32MemReg.cs
OpCode32MemRsImm.cs
OpCode32MemStEx.cs
OpCode32Sat.cs
OpCode32Sat16.cs
OpCode32Simd.cs
OpCode32SimdBase.cs
OpCode32SimdBinary.cs
OpCode32SimdCmpZ.cs
OpCode32SimdCvtFI.cs
OpCode32SimdDupElem.cs
OpCode32SimdDupGP.cs
OpCode32SimdExt.cs
OpCode32SimdImm.cs
OpCode32SimdImm44.cs	Add most of the A32 instruction set to ARMeilleure (#897)	2020-02-24 08:20:40 +11:00
OpCode32SimdLong.cs
OpCode32SimdMemImm.cs
OpCode32SimdMemMult.cs
OpCode32SimdMemPair.cs
OpCode32SimdMemSingle.cs
OpCode32SimdMovGp.cs
OpCode32SimdMovGpDouble.cs
OpCode32SimdMovGpElem.cs
OpCode32SimdReg.cs
OpCode32SimdRegElem.cs
OpCode32SimdRegElemLong.cs
OpCode32SimdRegLong.cs
OpCode32SimdRegS.cs
OpCode32SimdRegWide.cs
OpCode32SimdRev.cs
OpCode32SimdS.cs
OpCode32SimdSel.cs
OpCode32SimdShImm.cs
OpCode32SimdShImmNarrow.cs
OpCode32SimdSpecial.cs
OpCode32SimdSqrte.cs
OpCode32SimdTbl.cs
OpCode32System.cs
OpCodeAdr.cs
OpCodeAlu.cs
OpCodeAluBinary.cs
OpCodeAluImm.cs
OpCodeAluRs.cs
OpCodeAluRx.cs
OpCodeBfm.cs
OpCodeBImm.cs
OpCodeBImmAl.cs
OpCodeBImmCmp.cs
OpCodeBImmCond.cs
OpCodeBImmTest.cs
OpCodeBReg.cs
OpCodeCcmp.cs
OpCodeCcmpImm.cs
OpCodeCcmpReg.cs
OpCodeCsel.cs
OpCodeException.cs
OpCodeMem.cs
OpCodeMemEx.cs
OpCodeMemImm.cs
OpCodeMemLit.cs
OpCodeMemPair.cs
OpCodeMemReg.cs
OpCodeMov.cs
OpCodeMul.cs
OpCodeSimd.cs
OpCodeSimdCvt.cs
OpCodeSimdExt.cs
OpCodeSimdFcond.cs
OpCodeSimdFmov.cs
OpCodeSimdHelper.cs
OpCodeSimdImm.cs
OpCodeSimdIns.cs
OpCodeSimdMemImm.cs
OpCodeSimdMemLit.cs
OpCodeSimdMemMs.cs
OpCodeSimdMemPair.cs
OpCodeSimdMemReg.cs
OpCodeSimdMemSs.cs
OpCodeSimdReg.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
OpCodeSimdRegElem.cs
OpCodeSimdRegElemF.cs
OpCodeSimdShImm.cs
OpCodeSimdTbl.cs
OpCodeSystem.cs
OpCodeT16.cs
OpCodeT16AluImm8.cs
OpCodeT16BReg.cs
OpCodeTable.cs	Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192)	2020-07-19 15:11:58 -03:00
RegisterSize.cs
ShiftType.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00