Ryujinx/ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs

namespace ARMeilleure.Decoders
{
    class OpCode32SimdShImmNarrow : OpCode32SimdShImm
    {
        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmNarrow(inst, address, opCode);

        public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
    }
}
-												Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)

* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes

* Re-align opcode table

* Re-enable undefined, use subclasses to fix checks

* Add test and fix VRSHR instruction

* PR feedback
											
										
										
											2020-03-11 01:49:27 +01:00
+								namespace ARMeilleure.Decoders
 								{
 								    class OpCode32SimdShImmNarrow : OpCode32SimdShImm
 								    {
-												Get rid of Reflection.Emit dependency on CPU and Shader projects (#1626)

* Get rid of Reflection.Emit dependency on CPU and Shader projects

* Remove useless private sets

* Missed those due to the alignment
											
										
										
											2020-10-21 14:13:44 +02:00
+								        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmNarrow(inst, address, opCode);
-												Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)

* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes

* Re-align opcode table

* Re-enable undefined, use subclasses to fix checks

* Add test and fix VRSHR instruction

* PR feedback
											
										
										
											2020-03-11 01:49:27 +01:00
+								        public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
 								    }
 								}