From b13fbc25b8c0b7abdac52d481abbc5ba58166aca Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Tue, 27 Aug 2019 23:39:38 -0300 Subject: [PATCH 1/2] shader_ir/conversion: Implement F2I F16 Ra.H1 --- src/video_core/engines/shader_bytecode.h | 3 +-- src/video_core/shader/decode/conversion.cpp | 20 ++++++++++++++++---- 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index aaa1acea9..35201c8be 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -1006,7 +1006,7 @@ union Instruction { } iset; union { - BitField<41, 2, u64> selector; // i2i and i2f only + BitField<41, 2, u64> selector; BitField<45, 1, u64> negate_a; BitField<49, 1, u64> abs_a; BitField<10, 2, Register::Size> src_size; @@ -1031,7 +1031,6 @@ union Instruction { return static_cast(rounding.Value() & rounding_mask); } } f2f; - } conversion; union { diff --git a/src/video_core/shader/decode/conversion.cpp b/src/video_core/shader/decode/conversion.cpp index 8973fbefa..cf328aff8 100644 --- a/src/video_core/shader/decode/conversion.cpp +++ b/src/video_core/shader/decode/conversion.cpp @@ -22,7 +22,7 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) { case OpCode::Id::I2I_R: case OpCode::Id::I2I_C: case OpCode::Id::I2I_IMM: { - UNIMPLEMENTED_IF(instr.conversion.selector); + UNIMPLEMENTED_IF(instr.conversion.selector.Value()); UNIMPLEMENTED_IF(instr.conversion.dst_size != Register::Size::Word); UNIMPLEMENTED_IF(instr.alu.saturate_d); @@ -57,8 +57,8 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) { case OpCode::Id::I2F_R: case OpCode::Id::I2F_C: case OpCode::Id::I2F_IMM: { + UNIMPLEMENTED_IF(instr.conversion.selector.Value()); UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long); - UNIMPLEMENTED_IF(instr.conversion.selector); UNIMPLEMENTED_IF_MSG(instr.generates_cc, "Condition codes generation in I2F is not implemented"); @@ -93,6 +93,7 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) { case OpCode::Id::F2F_R: case OpCode::Id::F2F_C: case OpCode::Id::F2F_IMM: { + UNIMPLEMENTED_IF(instr.conversion.selector.Value()); UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long); UNIMPLEMENTED_IF(instr.conversion.src_size == Register::Size::Long); UNIMPLEMENTED_IF_MSG(instr.generates_cc, @@ -169,8 +170,19 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) { }(); if (instr.conversion.src_size == Register::Size::Short) { - // TODO: figure where extract is sey in the encoding - value = Operation(OperationCode::FCastHalf0, PRECISE, value); + const OperationCode cast = [instr] { + switch (instr.conversion.selector) { + case 0: + return OperationCode::FCastHalf0; + case 1: + return OperationCode::FCastHalf1; + default: + UNREACHABLE_MSG("Invalid selector={}", + static_cast(instr.conversion.selector)); + return OperationCode::FCastHalf0; + } + }(); + value = Operation(cast, NO_PRECISE, std::move(value)); } value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a); From e3534700d79aedd696f36430ea2a632506f2b1e3 Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Wed, 28 Aug 2019 16:09:33 -0300 Subject: [PATCH 2/2] shader_ir/conversion: Split int and float selector and implement F2F H1 --- src/video_core/engines/shader_bytecode.h | 9 +++++- src/video_core/shader/decode/conversion.cpp | 34 ++++++++++----------- 2 files changed, 24 insertions(+), 19 deletions(-) diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 35201c8be..747284700 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -1006,7 +1006,6 @@ union Instruction { } iset; union { - BitField<41, 2, u64> selector; BitField<45, 1, u64> negate_a; BitField<49, 1, u64> abs_a; BitField<10, 2, Register::Size> src_size; @@ -1031,6 +1030,14 @@ union Instruction { return static_cast(rounding.Value() & rounding_mask); } } f2f; + + union { + BitField<41, 2, u64> selector; + } int_src; + + union { + BitField<41, 1, u64> selector; + } float_src; } conversion; union { diff --git a/src/video_core/shader/decode/conversion.cpp b/src/video_core/shader/decode/conversion.cpp index cf328aff8..32facd6ba 100644 --- a/src/video_core/shader/decode/conversion.cpp +++ b/src/video_core/shader/decode/conversion.cpp @@ -14,6 +14,12 @@ using Tegra::Shader::Instruction; using Tegra::Shader::OpCode; using Tegra::Shader::Register; +namespace { +constexpr OperationCode GetFloatSelector(u64 selector) { + return selector == 0 ? OperationCode::FCastHalf0 : OperationCode::FCastHalf1; +} +} // Anonymous namespace + u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) { const Instruction instr = {program_code[pc]}; const auto opcode = OpCode::Decode(instr); @@ -22,7 +28,7 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) { case OpCode::Id::I2I_R: case OpCode::Id::I2I_C: case OpCode::Id::I2I_IMM: { - UNIMPLEMENTED_IF(instr.conversion.selector.Value()); + UNIMPLEMENTED_IF(instr.conversion.int_src.selector != 0); UNIMPLEMENTED_IF(instr.conversion.dst_size != Register::Size::Word); UNIMPLEMENTED_IF(instr.alu.saturate_d); @@ -57,7 +63,7 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) { case OpCode::Id::I2F_R: case OpCode::Id::I2F_C: case OpCode::Id::I2F_IMM: { - UNIMPLEMENTED_IF(instr.conversion.selector.Value()); + UNIMPLEMENTED_IF(instr.conversion.int_src.selector != 0); UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long); UNIMPLEMENTED_IF_MSG(instr.generates_cc, "Condition codes generation in I2F is not implemented"); @@ -93,7 +99,6 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) { case OpCode::Id::F2F_R: case OpCode::Id::F2F_C: case OpCode::Id::F2F_IMM: { - UNIMPLEMENTED_IF(instr.conversion.selector.Value()); UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long); UNIMPLEMENTED_IF(instr.conversion.src_size == Register::Size::Long); UNIMPLEMENTED_IF_MSG(instr.generates_cc, @@ -114,8 +119,10 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) { }(); if (instr.conversion.src_size == Register::Size::Short) { - // TODO: figure where extract is sey in the encoding - value = Operation(OperationCode::FCastHalf0, PRECISE, value); + value = Operation(GetFloatSelector(instr.conversion.float_src.selector), NO_PRECISE, + std::move(value)); + } else { + ASSERT(instr.conversion.float_src.selector == 0); } value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a); @@ -170,19 +177,10 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) { }(); if (instr.conversion.src_size == Register::Size::Short) { - const OperationCode cast = [instr] { - switch (instr.conversion.selector) { - case 0: - return OperationCode::FCastHalf0; - case 1: - return OperationCode::FCastHalf1; - default: - UNREACHABLE_MSG("Invalid selector={}", - static_cast(instr.conversion.selector)); - return OperationCode::FCastHalf0; - } - }(); - value = Operation(cast, NO_PRECISE, std::move(value)); + value = Operation(GetFloatSelector(instr.conversion.float_src.selector), NO_PRECISE, + std::move(value)); + } else { + ASSERT(instr.conversion.float_src.selector == 0); } value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);