diff --git a/src/common/host_memory.cpp b/src/common/host_memory.cpp index 14b4e4367..4f5a11f86 100644 --- a/src/common/host_memory.cpp +++ b/src/common/host_memory.cpp @@ -1,4 +1,5 @@ // SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project +// SPDX-FileCopyrightText: Copyright 2025 citron Emulator Project // SPDX-License-Identifier: GPL-2.0-or-later #ifdef _WIN32 @@ -720,10 +721,18 @@ void HostMemory::Map(size_t virtual_offset, size_t host_offset, size_t length, ASSERT(length % PageAlignment == 0); ASSERT(virtual_offset + length <= virtual_size); ASSERT(host_offset + length <= backing_size); + if (length == 0 || !virtual_base || !impl) { return; } + impl->Map(virtual_offset + virtual_base_offset, host_offset, length, perms); + + // Verify mapping was successful + if (!impl->IsValidMapping(virtual_offset + virtual_base_offset, length)) { + LOG_CRITICAL(Common_Memory, "Failed to verify memory mapping: virtual_offset={:x}, host_offset={:x}, length={:x}", + virtual_offset, host_offset, length); + } } void HostMemory::Unmap(size_t virtual_offset, size_t length, bool separate_heap) { @@ -756,9 +765,18 @@ void HostMemory::ClearBackingRegion(size_t physical_offset, size_t length, u32 f } void HostMemory::EnableDirectMappedAddress() { - if (impl) { - impl->EnableDirectMappedAddress(); + if (!impl) { + LOG_ERROR(Common_Memory, "Implementation not initialized"); + return; + } + + impl->EnableDirectMappedAddress(); + + // Only update virtual_size if the direct mapping was successful + if (impl->IsDirectMappingEnabled()) { virtual_size += reinterpret_cast(virtual_base); + } else { + LOG_ERROR(Common_Memory, "Failed to enable direct mapped address"); } } diff --git a/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp b/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp index ed14a3277..bbf77c5ad 100644 --- a/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp +++ b/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp @@ -1,4 +1,5 @@ // SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project +// SPDX-FileCopyrightText: Copyright 2025 citron Emulator Project // SPDX-License-Identifier: GPL-2.0-or-later #include @@ -45,6 +46,8 @@ NvResult nvhost_ctrl_gpu::Ioctl1(DeviceFD fd, Ioctl command, std::span return WrapFixed(this, &nvhost_ctrl_gpu::GetActiveSlotMask, input, output); case 0x1c: return WrapFixed(this, &nvhost_ctrl_gpu::GetGpuTime, input, output); + case 0x13: + return WrapFixed(this, &nvhost_ctrl_gpu::GetTpcMasks2, input, output); default: break; } @@ -261,6 +264,24 @@ NvResult nvhost_ctrl_gpu::GetGpuTime(IoctlGetGpuTime& params) { return NvResult::Success; } +NvResult nvhost_ctrl_gpu::GetTpcMasks2(IoctlGetTpcMasks& params) { + LOG_DEBUG(Service_NVDRV, "called, mask_buffer_size={}", params.mask_buf_size); + + // Validate input parameters + if (params.mask_buf_size == 0 || params.mask_buf_size > params.tpc_mask_buf.size()) { + LOG_ERROR(Service_NVDRV, "Invalid mask buffer size {}", params.mask_buf_size); + return NvResult::InvalidValue; + } + + // Set up TPC mask values based on GPU configuration + // Using conservative values for compatibility + params.mask_buf_size = 1; + params.tpc_mask_buf[0] = 0x1; // Enable first TPC only + + LOG_DEBUG(Service_NVDRV, "TPC mask set to 0x{:x}", params.tpc_mask_buf[0]); + return NvResult::Success; +} + Kernel::KEvent* nvhost_ctrl_gpu::QueryEvent(u32 event_id) { switch (event_id) { case 1: diff --git a/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.h b/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.h index 56e9fe22c..7258c362c 100644 --- a/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.h +++ b/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.h @@ -1,4 +1,5 @@ // SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project +// SPDX-FileCopyrightText: Copyright 2025 citron Emulator Project // SPDX-License-Identifier: GPL-2.0-or-later #pragma once @@ -34,6 +35,11 @@ public: Kernel::KEvent* QueryEvent(u32 event_id) override; + struct IoctlGetTpcMasks { + u32 mask_buf_size{}; + std::array tpc_mask_buf{}; + }; + private: static constexpr std::size_t MaxZBCTableSize = 16; static constexpr std::size_t MaxZBCFormats = 32; @@ -201,6 +207,8 @@ private: NvResult GetTPCMasks1(IoctlGpuGetTpcMasksArgs& params); NvResult GetTPCMasks3(IoctlGpuGetTpcMasksArgs& params, std::span tpc_mask); + NvResult GetTpcMasks2(IoctlGetTpcMasks& params); + NvResult GetActiveSlotMask(IoctlActiveSlotMask& params); NvResult ZCullGetCtxSize(IoctlZcullGetCtxSize& params); NvResult ZCullGetInfo(IoctlNvgpuGpuZcullGetInfoArgs& params);